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Searched refs:readw (Results 1 – 25 of 269) sorted by relevance

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/drivers/scsi/qla4xxx/
A Dql4_dbg.c46 readw(&ha->reg->mailbox[i])); in qla4xxx_dump_registers()
51 readw(&ha->reg->flash_address)); in qla4xxx_dump_registers()
54 readw(&ha->reg->flash_data)); in qla4xxx_dump_registers()
57 readw(&ha->reg->ctrl_status)); in qla4xxx_dump_registers()
62 readw(&ha->reg->u1.isp4010.nvram)); in qla4xxx_dump_registers()
66 readw(&ha->reg->u1.isp4022.intr_mask)); in qla4xxx_dump_registers()
69 readw(&ha->reg->u1.isp4022.nvram)); in qla4xxx_dump_registers()
76 readw(&ha->reg->req_q_in)); in qla4xxx_dump_registers()
79 readw(&ha->reg->rsp_q_out)); in qla4xxx_dump_registers()
96 readw(&ha->reg->u2.isp4010.gp_out)); in qla4xxx_dump_registers()
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/drivers/rtc/
A Drtc-msc313.c55 seconds = readw(priv->rtc_base + REG_RTC_MATCH_VAL_L) in msc313_rtc_read_alarm()
60 if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT)) in msc313_rtc_read_alarm()
71 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_alarm_irq_enable()
96 return readw(priv->rtc_base + REG_RTC_CTRL) & CNT_EN_BIT; in msc313_rtc_get_enabled()
103 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_enabled()
117 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_read_time()
121 while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT) in msc313_rtc_read_time()
124 seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L) in msc313_rtc_read_time()
143 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_time()
166 reg = readw(priv->rtc_base + REG_RTC_STATUS_INT); in msc313_rtc_interrupt()
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A Drtc-mxc.c96 day = readw(ioaddr + RTC_DAYR); in get_alarm_or_time()
97 hr_min = readw(ioaddr + RTC_HOURMIN); in get_alarm_or_time()
98 sec = readw(ioaddr + RTC_SECOND); in get_alarm_or_time()
101 day = readw(ioaddr + RTC_DAYALARM); in get_alarm_or_time()
102 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; in get_alarm_or_time()
103 sec = readw(ioaddr + RTC_ALRM_SEC); in get_alarm_or_time()
161 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); in rtc_update_alarm()
174 reg = readw(ioaddr + RTC_RTCIENR); in mxc_rtc_irq_enable()
195 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); in mxc_rtc_interrupt()
264 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; in mxc_rtc_read_alarm()
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A Drtc-ssd202d.c103 val = readw(priv->base + reg); in ssd202d_rtc_read_reg()
108 l = readw(priv->base + REG_RDDATA_L); in ssd202d_rtc_read_reg()
109 h = readw(priv->base + REG_RDDATA_H); in ssd202d_rtc_read_reg()
120 val = readw(priv->base + reg); in ssd202d_rtc_write_reg()
133 val = readw(priv->base + REG_CTRL1); in ssd202d_rtc_read_counter()
138 val = readw(priv->base + REG_CTRL1); in ssd202d_rtc_read_counter()
142 l = readw(priv->base + REG_RDCNT_L); in ssd202d_rtc_read_counter()
143 h = readw(priv->base + REG_RDCNT_H); in ssd202d_rtc_read_counter()
180 val = readw(priv->base + REG_CTRL); in ssd202d_rtc_reset_counter()
/drivers/scsi/arm/
A Dcumana_1.c130 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
131 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
132 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
133 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
134 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
135 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
136 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
137 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
/drivers/tty/
A Dmoxa.c506 ret = readw(ofsAddr + FuncArg); in moxafuncret()
516 rptr = readw(ofsAddr + RXrptr); in moxa_low_water_check()
517 wptr = readw(ofsAddr + RXwptr); in moxa_low_water_check()
1948 tail = readw(ofsAddr + TXwptr); in MoxaPortWriteData()
1949 head = readw(ofsAddr + TXrptr); in MoxaPortWriteData()
2002 head = readw(ofsAddr + RXrptr); in MoxaPortReadData()
2003 tail = readw(ofsAddr + RXwptr); in MoxaPortReadData()
2056 rptr = readw(ofsAddr + TXrptr); in MoxaPortTxQueue()
2057 wptr = readw(ofsAddr + TXwptr); in MoxaPortTxQueue()
2067 rptr = readw(ofsAddr + TXrptr); in MoxaPortTxFree()
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/drivers/input/keyboard/
A Dimx_keypad.c94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
113 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
127 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
135 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
294 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_irq_handler()
322 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_config()
328 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_config()
339 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_config()
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/drivers/media/pci/netup_unidvb/
A Dnetup_unidvb_i2c.c72 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
95 tmp = readw(&i2c->regs->rx_fifo.stat_ctrl); in netup_i2c_interrupt()
103 tmp = readw(&i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_interrupt()
135 (readw(&i2c->regs->tx_fifo.stat_ctrl) & 0x3f); in netup_i2c_fifo_tx()
148 writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_tx()
172 writew(readw(&i2c->regs->rx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_rx()
180 u16 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_start_xfer()
188 __func__, readw(&i2c->regs->length), in netup_i2c_start_xfer()
189 readw(&i2c->regs->twi_addr_ctrl1), in netup_i2c_start_xfer()
190 readw(&i2c->regs->twi_ctrl0_stat)); in netup_i2c_start_xfer()
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A Dnetup_unidvb_ci.c60 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
66 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
91 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_reset()
99 ci_stat = readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET); in netup_unidvb_ci_slot_reset()
123 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_poll_ci_slot_status()
124 ci_stat = readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET); in netup_unidvb_poll_ci_slot_status()
A Dnetup_unidvb_spi.c78 reg = readw(&spi->regs->control_stat); in netup_spi_interrupt()
86 reg = readw(&spi->regs->control_stat); in netup_spi_interrupt()
136 __func__, readw(&spi->regs->control_stat)); in netup_spi_transfer()
232 reg = readw(&spi->regs->control_stat); in netup_spi_release()
234 reg = readw(&spi->regs->control_stat); in netup_spi_release()
/drivers/i2c/busses/
A Di2c-viai2c-common.c10 while (!(readw(i2c->base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) { in viai2c_wait_bus_not_busy()
40 val = readw(i2c->base + VIAI2C_REG_CR); in viai2c_write()
53 val = readw(i2c->base + VIAI2C_REG_CR); in viai2c_write()
68 val = readw(i2c->base + VIAI2C_REG_CR); in viai2c_read()
87 val = readw(i2c->base + VIAI2C_REG_CR); in viai2c_read()
143 msg->buf[i2c->xfered_len] = readw(base + VIAI2C_REG_CDR) >> 8; in viai2c_irq_xfer()
145 val = readw(base + VIAI2C_REG_CR) | VIAI2C_CR_CPU_RDY; in viai2c_irq_xfer()
150 val = readw(base + VIAI2C_REG_CSR); in viai2c_irq_xfer()
/drivers/pci/
A Drom.c94 if (readw(image) != 0xAA55) { in pci_get_rom_size()
96 readw(image)); in pci_get_rom_size()
100 pds = image + readw(image + 24); in pci_get_rom_size()
107 length = readw(pds + 16); in pci_get_rom_size()
113 if (readw(image) != 0xAA55) { in pci_get_rom_size()
/drivers/net/ethernet/packetengines/
A Dhamachi.c832 return readw(ioaddr + MII_Rd_Data); in mdio_read()
985 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus)); in hamachi_open()
1039 readw(ioaddr + 0x0e0), in hamachi_timer()
1040 readw(ioaddr + 0x0e2), in hamachi_timer()
1041 readw(ioaddr + 0x0e4), in hamachi_timer()
1042 readw(ioaddr + 0x0e6), in hamachi_timer()
1043 readw(ioaddr + 0x0e8), in hamachi_timer()
1044 readw(ioaddr + 0x0eA)); in hamachi_timer()
1233 status=readw(hmp->base + TxStatus); in hamachi_start_xmit()
1273 status=readw(hmp->base + TxStatus); in hamachi_start_xmit()
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/drivers/comedi/drivers/
A Ddaqboard2000.c311 status = readw(dev->mmio + DB2K_REG_ACQ_STATUS); in db2k_ai_status()
372 data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO); in db2k_ai_insn_read()
388 status = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_ao_eoc()
470 cpld = readw(dev->mmio + DB2K_REG_CPLD_STATUS); in db2k_wait_cpld_init()
486 if (readw(dev->mmio + DB2K_REG_CPLD_STATUS) & in db2k_wait_cpld_txready()
507 if (!(readw(dev->mmio + DB2K_REG_CPLD_STATUS) & DB2K_CPLD_STATUS_INIT)) in db2k_write_cpld()
573 new_cpld = (readw(dev->mmio + DB2K_REG_CPLD_STATUS) & in db2k_load_firmware()
630 val = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_activate_reference_dacs()
640 val = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_activate_reference_dacs()
674 return readw(dev->mmio + iobase + port * 2); in db2k_8255_cb()
A Dme_daq.c202 val = readw(mmio_porta); in me_dio_insn_bits()
207 val |= (readw(mmio_portb) << 16); in me_dio_insn_bits()
221 status = readw(dev->mmio + ME_STATUS_REG); in me_ai_eoc()
273 readw(dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
281 val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata; in me_ai_insn_read()
322 readw(dev->mmio + ME_DAC_CTRL_REG); in me_ao_insn_write()
333 readw(dev->mmio + ME_CTRL2_REG); in me_ao_insn_write()
351 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET); in me2600_xilinx_download()
/drivers/dma/ioat/
A Ddca.c139 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_add_requester()
165 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_remove_requester()
220 global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_count_dca_slots()
272 dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); in ioat_dca_init()
291 csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); in ioat_dca_init()
297 pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); in ioat_dca_init()
/drivers/pwm/
A Dpwm-tiecap.c74 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
96 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
115 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_set_polarity()
143 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_enable()
159 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_disable()
276 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2); in ecap_pwm_save_context()
/drivers/spi/
A Dspi-pl022.c432 tmp = readw(SSP_CSR(pl022->virtbase)); in internal_cs_control()
458 readw(SSP_DR(pl022->virtbase)); in flush()
604 readw(SSP_DR(pl022->virtbase)); in readwriter()
608 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
612 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
653 readw(SSP_DR(pl022->virtbase)); in readwriter()
657 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
661 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
1172 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_interrupt_handler()
1284 read_sr = readw(SSP_SR(pl022->virtbase)); in print_current_status()
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/drivers/pci/controller/
A Dpci-v3-semi.c442 status = readw(v3->base + V3_PCI_STAT); in v3_irq()
778 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) in v3_pci_probe()
782 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
787 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
792 val = readw(v3->base + V3_PCI_CFG); in v3_pci_probe()
797 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
805 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
853 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
867 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
878 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
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/drivers/watchdog/
A Dmenz69_wdt.c39 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_start()
51 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_stop()
64 val = readw(drv->base + MEN_Z069_WVR); in men_z069_wdt_ping()
80 reg = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_set_timeout()
/drivers/atm/
A Diphase.c1033 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1039 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1040 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1072 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1507 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1616 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
2023 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2050 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2079 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2080 readw(iadev->seg_reg+CBR_TAB_END+1));)
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/drivers/gpu/drm/nouveau/dispnv50/
A Dheadc57d.c160 writew(readw(mem - 8), mem + 0); in headc57d_olut_load_8()
161 writew(readw(mem - 6), mem + 2); in headc57d_olut_load_8()
162 writew(readw(mem - 4), mem + 4); in headc57d_olut_load_8()
180 writew(readw(mem - 8), mem + 0); in headc57d_olut_load()
181 writew(readw(mem - 6), mem + 2); in headc57d_olut_load()
182 writew(readw(mem - 4), mem + 4); in headc57d_olut_load()
/drivers/mmc/host/
A Dsdhci-pxav2.c68 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
80 tmp = readw(host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
84 tmp = readw(host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
98 return readw(host->ioaddr + reg); in pxav1_readw()
133 tmp = readw(host->ioaddr + SDHCI_TIMEOUT_CONTROL); in pxav1_request_done()
163 tmp = readw(host->ioaddr + SD_CE_ATA_2); in pxav2_mmc_set_bus_width()
/drivers/thermal/intel/
A Dintel_pch_thermal.c125 *temp = GET_WPT_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP)); in pch_thermal_get_temp()
222 trip_temp = readw(ptd->hw_base + WPT_CTT); in intel_pch_thermal_probe()
229 trip_temp = readw(ptd->hw_base + WPT_PHL); in intel_pch_thermal_probe()
296 pch_thr_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TSPM)); in intel_pch_thermal_suspend_noirq()
299 pch_cur_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP)); in intel_pch_thermal_suspend_noirq()
329 pch_cur_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP)); in intel_pch_thermal_suspend_noirq()
/drivers/usb/musb/
A Dsunxi.c191 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); in sunxi_musb_interrupt()
195 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); in sunxi_musb_interrupt()
542 return readw(addr + SUNXI_MUSB_INTRTX); in sunxi_musb_readw()
544 return readw(addr + SUNXI_MUSB_INTRRX); in sunxi_musb_readw()
546 return readw(addr + SUNXI_MUSB_INTRTXE); in sunxi_musb_readw()
548 return readw(addr + SUNXI_MUSB_INTRRXE); in sunxi_musb_readw()
550 return readw(addr + SUNXI_MUSB_FRAME); in sunxi_musb_readw()
552 return readw(addr + SUNXI_MUSB_TXFIFOADD); in sunxi_musb_readw()
554 return readw(addr + SUNXI_MUSB_RXFIFOADD); in sunxi_musb_readw()
564 return readw(addr + offset); in sunxi_musb_readw()
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