| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 240 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn201_init_hw()
246 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn201_init_hw()
249 res_pool->ref_clocks.dccg_ref_clock_inKhz, in dcn201_init_hw()
250 &res_pool->ref_clocks.dchub_ref_clock_inKhz); in dcn201_init_hw()
252 res_pool->ref_clocks.dccg_ref_clock_inKhz = in dcn201_init_hw()
253 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn201_init_hw()
254 res_pool->ref_clocks.dchub_ref_clock_inKhz = in dcn201_init_hw()
255 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn201_init_hw()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| A D | dcn31_hwseq.c | 134 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn31_init_hw()
141 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn31_init_hw()
144 res_pool->ref_clocks.dccg_ref_clock_inKhz, in dcn31_init_hw()
145 &res_pool->ref_clocks.dchub_ref_clock_inKhz); in dcn31_init_hw()
148 res_pool->ref_clocks.dccg_ref_clock_inKhz = in dcn31_init_hw()
149 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn31_init_hw()
150 res_pool->ref_clocks.dchub_ref_clock_inKhz = in dcn31_init_hw()
151 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn31_init_hw()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| A D | dcn30_hwseq.c | 679 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn30_init_hw()
686 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn30_init_hw()
689 res_pool->ref_clocks.dccg_ref_clock_inKhz, in dcn30_init_hw()
690 &res_pool->ref_clocks.dchub_ref_clock_inKhz); in dcn30_init_hw()
693 res_pool->ref_clocks.dccg_ref_clock_inKhz = in dcn30_init_hw()
694 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn30_init_hw()
695 res_pool->ref_clocks.dchub_ref_clock_inKhz = in dcn30_init_hw()
696 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn30_init_hw()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 157 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn35_init_hw()
164 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn35_init_hw()
167 res_pool->ref_clocks.dccg_ref_clock_inKhz, in dcn35_init_hw()
168 &res_pool->ref_clocks.dchub_ref_clock_inKhz); in dcn35_init_hw()
171 res_pool->ref_clocks.dccg_ref_clock_inKhz = in dcn35_init_hw()
172 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn35_init_hw()
173 res_pool->ref_clocks.dchub_ref_clock_inKhz = in dcn35_init_hw()
174 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn35_init_hw()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 811 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn32_init_hw()
817 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn32_init_hw()
820 res_pool->ref_clocks.dccg_ref_clock_inKhz, in dcn32_init_hw()
821 &res_pool->ref_clocks.dchub_ref_clock_inKhz); in dcn32_init_hw()
824 res_pool->ref_clocks.dccg_ref_clock_inKhz = in dcn32_init_hw()
825 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn32_init_hw()
826 res_pool->ref_clocks.dchub_ref_clock_inKhz = in dcn32_init_hw()
827 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn32_init_hw()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 173 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn401_init_hw()
179 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn401_init_hw()
181 current_dchub_ref_freq = res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn401_init_hw()
184 res_pool->ref_clocks.dccg_ref_clock_inKhz, in dcn401_init_hw()
185 &res_pool->ref_clocks.dchub_ref_clock_inKhz); in dcn401_init_hw()
188 res_pool->ref_clocks.dccg_ref_clock_inKhz = in dcn401_init_hw()
189 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn401_init_hw()
190 res_pool->ref_clocks.dchub_ref_clock_inKhz = in dcn401_init_hw()
191 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn401_init_hw()
1386 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, in dcn401_prepare_bandwidth()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_panel_cntl.c | 101 uint32_t xtal = panel_cntl->ctx->dc->res_pool->ref_clocks.dccg_ref_clock_inKhz; in dcn31_panel_cntl_hw_init()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 88 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
1757 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn10_init_hw()
1764 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn10_init_hw()
1767 res_pool->ref_clocks.dccg_ref_clock_inKhz, in dcn10_init_hw()
1768 &res_pool->ref_clocks.dchub_ref_clock_inKhz); in dcn10_init_hw()
1771 res_pool->ref_clocks.dccg_ref_clock_inKhz = in dcn10_init_hw()
1772 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn10_init_hw()
1773 res_pool->ref_clocks.dchub_ref_clock_inKhz = in dcn10_init_hw()
1774 res_pool->ref_clocks.xtalin_clock_inKhz; in dcn10_init_hw()
3317 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, in dcn10_prepare_bandwidth()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer_debug.c | 81 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
119 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn30/ |
| A D | dcn30_hubbub.c | 382 uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in hubbub3_force_wm_propagate_to_pipes()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 297 } ref_clocks; member
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 339 res_pool->ref_clocks.xtalin_clock_inKhz = in dc_create_resource_pool()
347 res_pool->ref_clocks.dccg_ref_clock_inKhz = in dc_create_resource_pool()
348 res_pool->ref_clocks.xtalin_clock_inKhz; in dc_create_resource_pool()
349 res_pool->ref_clocks.dchub_ref_clock_inKhz = in dc_create_resource_pool()
350 res_pool->ref_clocks.xtalin_clock_inKhz; in dc_create_resource_pool()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1368 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_populate_dml_pipes_from_context()
1746 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_calculate_wm()
2256 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn21_calculate_wm()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| A D | dcn321_fpu.c | 705 …dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz … in dcn321_update_bw_bounding_box_fpu()
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn32/ |
| A D | dcn32_hubbub.c | 941 uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in hubbub32_force_wm_propagate_to_pipes()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 70 dml_init->soc_bb.dchub_refclk_mhz = in_dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in override_dml_init_with_values_from_hardware_default()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 2398 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, in dcn20_prepare_bandwidth()
2439 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, in dcn20_optimize_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 497 input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dmub_srv.c | 936 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; in dc_dmub_setup_subvp_dmub_command()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| A D | dce110_hwseq.c | 3119 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, in dce110_set_cursor_position()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 3147 …dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz … in dcn32_update_bw_bounding_box_fpu()
|