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Searched refs:refclk (Results 1 – 25 of 79) sorted by relevance

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/drivers/gpu/drm/i915/display/
A Dintel_cdclk.c1313 u16 refclk; member
1319 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1320 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1321 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1322 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1554 for (i = 0; table[i].refclk; i++) in bxt_calc_cdclk()
1555 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk()
1573 for (i = 0; table[i].refclk; i++) in bxt_calc_cdclk_pll_vco()
1574 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1928 for (i = 0; table[i].refclk; i++) in cdclk_squash_waveform()
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A Dintel_dpll.c522 int refclk = 100000; in vlv_crtc_clock_get() local
552 int refclk = 100000; in chv_crtc_clock_get() local
980 int refclk = 100000; in bxt_find_best_dpll() local
1534 int refclk = 96000; in g4x_crtc_compute_clock() local
1541 refclk); in g4x_crtc_compute_clock()
1583 int refclk = 96000; in pnv_crtc_compute_clock() local
1590 refclk); in pnv_crtc_compute_clock()
1621 int refclk = 96000; in i9xx_crtc_compute_clock() local
1628 refclk); in i9xx_crtc_compute_clock()
1661 int refclk = 48000; in i8xx_crtc_compute_clock() local
[all …]
A Dintel_snps_hdmi_pll.c131 static void compute_hdmi_tmds_pll(u64 pixel_clock, u32 refclk, in compute_hdmi_tmds_pll() argument
148 u32 refclk_postscalar = refclk >> prescaler_divider; in compute_hdmi_tmds_pll()
252 u32 refclk = 100000000; in intel_snps_hdmi_pll_compute_mpllb() local
258 compute_hdmi_tmds_pll(pixel_clock, refclk, ref_range, ana_cp_int_gs, ana_cp_prop_gs, in intel_snps_hdmi_pll_compute_mpllb()
323 u32 refclk = 38400000; in intel_snps_hdmi_pll_compute_c10pll() local
329 compute_hdmi_tmds_pll(pixel_clock, refclk, ref_range, in intel_snps_hdmi_pll_compute_c10pll()
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dpllgt215.c42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
51 fN = tmp % info->refclk; in gt215_pll_calc()
54 if (fN >= info->refclk / 2) in gt215_pll_calc()
57 if (fN < info->refclk / 2) in gt215_pll_calc()
59 fN = tmp - (N * info->refclk); in gt215_pll_calc()
67 err = abs(freq - (info->refclk * N / M / *P)); in gt215_pll_calc()
75 *pfN = ((fN << 13) + info->refclk / 2) / info->refclk; in gt215_pll_calc()
86 return info->refclk * *pN / *pM / *P; in gt215_pll_calc()
/drivers/phy/ti/
A Dphy-dm816x-usb.c46 struct clk *refclk; member
76 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
123 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_suspend()
134 error = clk_enable(phy->refclk); in dm816x_usb_phy_runtime_resume()
151 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_resume()
218 phy->refclk = devm_clk_get(phy->dev, "refclk"); in dm816x_usb_phy_probe()
219 if (IS_ERR(phy->refclk)) in dm816x_usb_phy_probe()
220 return PTR_ERR(phy->refclk); in dm816x_usb_phy_probe()
221 error = clk_prepare(phy->refclk); in dm816x_usb_phy_probe()
247 clk_unprepare(phy->refclk); in dm816x_usb_phy_probe()
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A Dphy-ti-pipe3.c172 struct clk *refclk; member
609 if (IS_ERR(phy->refclk)) { in ti_pipe3_get_clk()
615 return PTR_ERR(phy->refclk); in ti_pipe3_get_clk()
820 if (!IS_ERR(phy->refclk)) { in ti_pipe3_probe()
821 clk_prepare_enable(phy->refclk); in ti_pipe3_probe()
843 clk_disable_unprepare(phy->refclk); in ti_pipe3_remove()
853 if (!IS_ERR(phy->refclk)) { in ti_pipe3_enable_clocks()
884 if (!IS_ERR(phy->refclk)) in ti_pipe3_enable_clocks()
885 clk_disable_unprepare(phy->refclk); in ti_pipe3_enable_clocks()
894 if (!IS_ERR(phy->refclk)) in ti_pipe3_disable_clocks()
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/drivers/phy/xilinx/
A Dphy-zynqmp.c215 unsigned int refclk; member
406 clk = gtr_phy->dev->clk[gtr_phy->refclk]; in xpsgtr_find_sscs()
418 rate, gtr_phy->refclk); in xpsgtr_find_sscs()
439 if (gtr_phy->refclk == gtr_phy->lane) in xpsgtr_configure_pll()
825 unsigned int refclk; in xpsgtr_xlate() local
855 refclk = args->args[3]; in xpsgtr_xlate()
861 gtr_phy->refclk = refclk; in xpsgtr_xlate()
958 unsigned int refclk; in xpsgtr_get_ref_clocks() local
960 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->clk); ++refclk) { in xpsgtr_get_ref_clocks()
969 refclk); in xpsgtr_get_ref_clocks()
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/drivers/net/ethernet/arc/
A Demac_rockchip.c32 struct clk *refclk; member
147 priv->refclk = devm_clk_get(dev, "macref"); in emac_rockchip_probe()
148 if (IS_ERR(priv->refclk)) { in emac_rockchip_probe()
150 PTR_ERR(priv->refclk)); in emac_rockchip_probe()
151 err = PTR_ERR(priv->refclk); in emac_rockchip_probe()
155 err = clk_prepare_enable(priv->refclk); in emac_rockchip_probe()
195 err = clk_set_rate(priv->refclk, 50000000); in emac_rockchip_probe()
241 clk_disable_unprepare(priv->refclk); in emac_rockchip_probe()
254 clk_disable_unprepare(priv->refclk); in emac_rockchip_remove()
/drivers/gpu/drm/gma500/
A Dcdv_intel_display.c365 int refclk) in cdv_intel_limit() argument
373 if (refclk == 96000) in cdv_intel_limit()
379 if (refclk == 27000) in cdv_intel_limit()
384 if (refclk == 27000) in cdv_intel_limit()
403 int refclk, in cdv_intel_find_dp_pll() argument
411 switch (refclk) { in cdv_intel_find_dp_pll()
582 int refclk; in cdv_intel_crtc_mode_set() local
629 refclk = 96000; in cdv_intel_crtc_mode_set()
632 refclk = 27000; in cdv_intel_crtc_mode_set()
643 refclk = 27000; in cdv_intel_crtc_mode_set()
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A Dgma_display.h44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
88 struct drm_crtc *crtc, int target, int refclk,
A Doaktrail_crtc.c41 int refclk, struct gma_clock_t *best_clock);
45 int refclk, struct gma_clock_t *best_clock);
84 int refclk) in mrst_limit() argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
128 int refclk, struct gma_clock_t *best_clock) in mrst_sdvo_find_best_pll() argument
153 actual_freq = (refclk * clock.m) / in mrst_sdvo_find_best_pll()
186 int refclk, struct gma_clock_t *best_clock) in mrst_lvds_find_best_pll() argument
199 mrst_lvds_clock(refclk, &clock); in mrst_lvds_find_best_pll()
370 int refclk = 0; in oaktrail_crtc_mode_set() local
506 limit = mrst_limit(crtc, refclk); in oaktrail_crtc_mode_set()
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A Dpsb_intel_display.c57 int refclk) in psb_intel_limit() argument
68 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) in psb_intel_clock() argument
72 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
105 int refclk; in psb_intel_crtc_mode_set() local
144 refclk = 96000; in psb_intel_crtc_mode_set()
146 limit = gma_crtc->clock_funcs->limit(crtc, refclk); in psb_intel_crtc_mode_set()
148 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in psb_intel_crtc_mode_set()
A Doaktrail_hdmi.c179 int refclk, struct oaktrail_hdmi_clock *best_clock) in oaktrail_hdmi_find_dpll() argument
191 nr_min = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_max)); in oaktrail_hdmi_find_dpll()
192 nr_max = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_min)); in oaktrail_hdmi_find_dpll()
198 np = DIV_ROUND_UP((refclk * 1000), (target * 10 * nr_max)); in oaktrail_hdmi_find_dpll()
199 nr = DIV_ROUND_UP((refclk * 1000), (target * 10 * np)); in oaktrail_hdmi_find_dpll()
200 nf = DIV_ROUND_CLOSEST((target * 10 * np * nr), refclk); in oaktrail_hdmi_find_dpll()
283 int refclk; in oaktrail_crtc_hdmi_mode_set() local
307 refclk = 25000; in oaktrail_crtc_hdmi_mode_set()
308 oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock); in oaktrail_crtc_hdmi_mode_set()
/drivers/spi/
A Dspi-zynq-qspi.c136 struct clk *refclk; member
350 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > in zynq_qspi_config_op()
389 ret = clk_enable(qspi->refclk); in zynq_qspi_setup_op()
395 clk_disable(qspi->refclk); in zynq_qspi_setup_op()
673 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); in zynq_qspi_probe()
674 if (IS_ERR(xqspi->refclk)) { in zynq_qspi_probe()
676 ret = PTR_ERR(xqspi->refclk); in zynq_qspi_probe()
686 ret = clk_prepare_enable(xqspi->refclk); in zynq_qspi_probe()
722 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; in zynq_qspi_probe()
737 clk_disable_unprepare(xqspi->refclk); in zynq_qspi_probe()
[all …]
A Dspi-zynqmp-gqspi.c193 struct clk *refclk; member
293 clk_rate = clk_get_rate(xqspi->refclk); in zynqmp_qspi_set_tapdelay()
402 clk_rate = clk_get_rate(xqspi->refclk); in zynqmp_qspi_init_hw()
567 clk_rate = clk_get_rate(xqspi->refclk); in zynqmp_qspi_config_op()
986 clk_disable_unprepare(xqspi->refclk); in zynqmp_runtime_suspend()
1011 ret = clk_prepare_enable(xqspi->refclk); in zynqmp_runtime_resume()
1253 if (IS_ERR(xqspi->refclk)) in zynqmp_qspi_probe()
1254 return dev_err_probe(dev, PTR_ERR(xqspi->refclk), in zynqmp_qspi_probe()
1261 ret = clk_prepare_enable(xqspi->refclk); in zynqmp_qspi_probe()
1342 clk_disable_unprepare(xqspi->refclk); in zynqmp_qspi_probe()
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/drivers/net/ethernet/ti/
A Dcpts.c559 err = clk_enable(cpts->refclk); in cpts_register()
580 clk_disable(cpts->refclk); in cpts_register()
600 clk_disable(cpts->refclk); in cpts_unregister()
609 freq = clk_get_rate(cpts->refclk); in cpts_calc_mult_shift()
768 if (IS_ERR(cpts->refclk)) in cpts_create()
772 if (IS_ERR(cpts->refclk)) { in cpts_create()
774 PTR_ERR(cpts->refclk)); in cpts_create()
775 return ERR_CAST(cpts->refclk); in cpts_create()
778 ret = clk_prepare(cpts->refclk); in cpts_create()
805 if (WARN_ON(!cpts->refclk)) in cpts_release()
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/drivers/phy/
A Dphy-pistachio-usb.c38 unsigned int refclk; member
68 p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT); in pistachio_usb_phy_power_on()
71 if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) { in pistachio_usb_phy_power_on()
161 &p_phy->refclk); in pistachio_usb_phy_probe()
/drivers/media/i2c/
A Dtc358746.c150 struct clk *refclk; member
915 unsigned long refclk, in tc358746_find_pll_settings() argument
946 fin = DIV_ROUND_CLOSEST(refclk, p); in tc358746_find_pll_settings()
1515 unsigned long refclk; in tc358746_probe() local
1529 if (IS_ERR(tc358746->refclk)) in tc358746_probe()
1538 refclk = clk_get_rate(tc358746->refclk); in tc358746_probe()
1539 clk_disable_unprepare(tc358746->refclk); in tc358746_probe()
1541 if (refclk < 6 * HZ_PER_MHZ || refclk > 40 * HZ_PER_MHZ) in tc358746_probe()
1637 clk_prepare_enable(tc358746->refclk); in tc358746_clk_enable()
1645 clk_disable_unprepare(tc358746->refclk); in tc358746_suspend()
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/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
A Dpll.c327 info->refclk = nvbios_rd32(bios, data + 31); in nvbios_pll_parse()
350 info->refclk = nvbios_rd32(bios, data + 28); in nvbios_pll_parse()
353 info->refclk = nvbios_rd16(bios, data + 9) * 1000; in nvbios_pll_parse()
368 info->refclk = nvbios_rd16(bios, data + 1) * 1000; in nvbios_pll_parse()
386 if (!info->refclk) { in nvbios_pll_parse()
387 info->refclk = device->crystal; in nvbios_pll_parse()
393 info->refclk = 200000; in nvbios_pll_parse()
395 info->refclk = 25000; in nvbios_pll_parse()
/drivers/gpu/drm/bridge/
A Dchipone-icn6211.c155 struct clk *refclk; member
279 if (icn->refclk) in chipone_configure_pll()
329 min_delta, icn->refclk ? "EXT" : "DSI", fin, in chipone_configure_pll()
338 icn->refclk ? PLL_CTRL_6_EXTERNAL : PLL_CTRL_6_MIPI_CLK); in chipone_configure_pll()
473 ret = clk_prepare_enable(icn->refclk); in chipone_atomic_pre_enable()
488 clk_disable_unprepare(icn->refclk); in chipone_atomic_post_disable()
635 icn->refclk = devm_clk_get_optional(dev, "refclk"); in chipone_parse_dt()
636 if (IS_ERR(icn->refclk)) { in chipone_parse_dt()
637 ret = PTR_ERR(icn->refclk); in chipone_parse_dt()
640 } else if (icn->refclk) { in chipone_parse_dt()
[all …]
A Dtc358768.c146 struct clk *refclk; member
267 ret = clk_prepare_enable(priv->refclk); in tc358768_hw_enable()
308 clk_disable_unprepare(priv->refclk); in tc358768_hw_disable()
334 unsigned long refclk; in tc358768_calc_pll() local
353 refclk = clk_get_rate(priv->refclk); in tc358768_calc_pll()
367 pll = (u32)div_u64((u64)refclk * fbd, divisor); in tc358768_calc_pll()
372 pll_in = (u32)div_u64((u64)refclk, prd); in tc358768_calc_pll()
632 clk_get_rate(priv->refclk), fbd, prd, frs); in tc358768_setup_pll()
1302 priv->refclk = devm_clk_get(dev, "refclk"); in tc358768_i2c_probe()
1303 if (IS_ERR(priv->refclk)) in tc358768_i2c_probe()
[all …]
A Dtc358767.c390 struct clk *refclk; member
623 refclk); in tc_pxl_pll_calc()
631 if (refclk / ext_div[i_pre] < 1000000) in tc_pxl_pll_calc()
639 iclk = refclk / (div * ext_div[i_pre]); in tc_pxl_pll_calc()
645 do_div(tmp, refclk); in tc_pxl_pll_calc()
652 clk = (refclk / ext_div[i_pre] / div) * mul; in tc_pxl_pll_calc()
758 rate = clk_get_rate(tc->refclk); in tc_set_syspllparam()
2477 tc->refclk = devm_clk_get_enabled(dev, "ref"); in tc_probe()
2478 if (IS_ERR(tc->refclk)) in tc_probe()
2479 return dev_err_probe(dev, PTR_ERR(tc->refclk), in tc_probe()
[all …]
/drivers/pci/controller/cadence/
A Dpci-j721e.c58 struct clk *refclk; member
591 pcie->refclk = clk; in j721e_pcie_probe()
607 clk_disable_unprepare(pcie->refclk); in j721e_pcie_probe()
656 clk_disable_unprepare(pcie->refclk); in j721e_pcie_remove()
669 clk_disable_unprepare(pcie->refclk); in j721e_pcie_suspend_noirq()
700 ret = clk_prepare_enable(pcie->refclk); in j721e_pcie_resume_noirq()
718 clk_disable_unprepare(pcie->refclk); in j721e_pcie_resume_noirq()
731 clk_disable_unprepare(pcie->refclk); in j721e_pcie_resume_noirq()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
A Dpll.h20 int refclk; member
47 u32 refclk; member
/drivers/phy/qualcomm/
A Dphy-qcom-sgmii-eth.c30 struct clk *refclk; member
271 return clk_prepare_enable(data->refclk); in qcom_dwmac_sgmii_phy_power_on()
284 clk_disable_unprepare(data->refclk); in qcom_dwmac_sgmii_phy_power_off()
342 data->refclk = devm_clk_get(dev, "sgmi_ref"); in qcom_dwmac_sgmii_phy_probe()
343 if (IS_ERR(data->refclk)) in qcom_dwmac_sgmii_phy_probe()
344 return PTR_ERR(data->refclk); in qcom_dwmac_sgmii_phy_probe()

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