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Searched refs:reg1 (Results 1 – 25 of 112) sorted by relevance

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/drivers/rtc/
A Drtc-aspeed.c25 u32 reg1, reg2; in aspeed_rtc_read_time() local
34 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
37 tm->tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_read_time()
38 tm->tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_read_time()
39 tm->tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_read_time()
40 tm->tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_read_time()
55 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
61 reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | in aspeed_rtc_set_time()
70 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
/drivers/gpu/drm/i915/display/
A Dintel_pmdemand.c404 u32 reg1, reg2; in intel_pmdemand_init_pmdemand_params() local
422 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
424 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
428 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
437 REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
440 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
442 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
519 u32 *reg1, u32 *reg2, bool serialized) in intel_pmdemand_update_params() argument
578 u32 reg1, mod_reg1; in intel_pmdemand_program_params() local
587 mod_reg1 = reg1; in intel_pmdemand_program_params()
[all …]
/drivers/media/dvb-frontends/
A Da8293.c29 u8 reg0, reg1; in a8293_set_voltage_slew() local
125 reg1 = 0x82; in a8293_set_voltage_slew()
126 if (reg1 != dev->reg[1]) { in a8293_set_voltage_slew()
127 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage_slew()
130 dev->reg[1] = reg1; in a8293_set_voltage_slew()
148 u8 reg0, reg1; in a8293_set_voltage_noslew() local
178 reg1 = 0x82; in a8293_set_voltage_noslew()
179 if (reg1 != dev->reg[1]) { in a8293_set_voltage_noslew()
180 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage_noslew()
183 dev->reg[1] = reg1; in a8293_set_voltage_noslew()
A Dtua6100.c64 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; in tua6100_set_params() local
67 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; in tua6100_set_params()
82 reg1[1] = 0x2c; in tua6100_set_params()
84 reg1[1] = 0x0c; in tua6100_set_params()
87 reg1[1] |= 0x40; in tua6100_set_params()
89 reg1[1] |= 0x80; in tua6100_set_params()
107 reg1[1] |= (div >> 9) & 0x03; in tua6100_set_params()
108 reg1[2] = div >> 1; in tua6100_set_params()
109 reg1[3] = (div << 7); in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
A Dsi21xx.c222 static int si21_writeregs(struct si21xx_state *state, u8 reg1, in si21_writeregs() argument
237 msg.buf[0] = reg1; in si21_writeregs()
244 __func__, reg1, data[0], ret); in si21_writeregs()
307 static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len) in si21_readregs() argument
314 .buf = &reg1, in si21_readregs()
479 u8 reg1; in si21xx_init() local
486 reg1 = serit_sp1511lhb_inittab[i]; in si21xx_init()
488 if (reg1 == 0xff && val == 0xff) in si21xx_init()
490 si21_writeregs(state, reg1, &val, 1); in si21xx_init()
494 reg1 = 0x08; in si21xx_init()
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/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
187 .enable_reg = SRI(reg1, block, reg_num),\
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
201 .enable_reg = SRI_DMUB(reg1),\
203 reg1 ## __ ## mask1 ## _MASK,\
205 reg1 ## __ ## mask1 ## _MASK,\
206 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
182 .enable_reg = SRI(reg1, block, reg_num),\
184 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
186 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
195 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
196 .enable_reg = SRI_DMUB(reg1),\
198 reg1 ## __ ## mask1 ## _MASK,\
200 reg1 ## __ ## mask1 ## _MASK,\
201 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn314/
A Dirq_service_dcn314.c183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
184 .enable_reg = SRI(reg1, block, reg_num),\
186 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
188 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
189 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
197 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
198 .enable_reg = SRI_DMUB(reg1),\
200 reg1 ## __ ## mask1 ## _MASK,\
202 reg1 ## __ ## mask1 ## _MASK,\
203 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn315/
A Dirq_service_dcn315.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 .enable_reg = SRI(reg1, block, reg_num),\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
203 .enable_reg = SRI_DMUB(reg1),\
205 reg1 ## __ ## mask1 ## _MASK,\
207 reg1 ## __ ## mask1 ## _MASK,\
208 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 .enable_reg = SRI(reg1, block, reg_num),\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
208 .enable_reg = SRI_DMUB(reg1),\
210 reg1 ## __ ## mask1 ## _MASK,\
212 reg1 ## __ ## mask1 ## _MASK,\
213 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
179 .enable_reg = SRI(reg1, block, reg_num),\
180 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
182 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
183 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
197 .enable_reg = SRI_DMUB(reg1),\
199 reg1 ## __ ## mask1 ## _MASK,\
201 reg1 ## __ ## mask1 ## _MASK,\
202 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dnv04.c49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog() argument
57 if (reg1 > 0x405c) in nv04_clk_pll_prog()
58 setPLL_double_highregs(devinit, reg1, pv); in nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); in nv04_clk_pll_prog()
62 setPLL_single(devinit, reg1, pv); in nv04_clk_pll_prog()
/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
160 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
162 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
164 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
166 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
174 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
176 reg1 ## __ ## mask1 ## _MASK,\
178 reg1 ## __ ## mask1 ## _MASK,\
180 ~reg1 ## __ ## mask1 ## _MASK, \
/drivers/gpu/drm/amd/display/dc/irq/dcn401/
A Dirq_service_dcn401.c172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
173 .enable_reg = SRI(reg1, block, reg_num),\
175 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
177 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
178 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
187 .enable_reg = SRI_DMUB(reg1),\
189 reg1 ## __ ## mask1 ## _MASK,\
191 reg1 ## __ ## mask1 ## _MASK,\
192 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn32/
A Dirq_service_dcn32.c192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
193 .enable_reg = SRI(reg1, block, reg_num),\
195 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
206 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
207 .enable_reg = SRI_DMUB(reg1),\
209 reg1 ## __ ## mask1 ## _MASK,\
211 reg1 ## __ ## mask1 ## _MASK,\
212 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
181 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
183 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
185 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
194 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
195 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
197 reg1 ## __ ## mask1 ## _MASK,\
199 reg1 ## __ ## mask1 ## _MASK,\
201 ~reg1 ## __ ## mask1 ## _MASK, \
/drivers/gpu/drm/amd/display/dc/irq/dcn36/
A Dirq_service_dcn36.c158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
159 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
161 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
163 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
165 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
173 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
175 reg1 ## __ ## mask1 ## _MASK,\
177 reg1 ## __ ## mask1 ## _MASK,\
179 ~reg1 ## __ ## mask1 ## _MASK, \
/drivers/mcb/
A Dmcb-parse.c42 __le32 reg1; in chameleon_parse_gdd() local
49 reg1 = readl(&gdd->reg1); in chameleon_parse_gdd()
54 mdev->id = GDD_DEV(reg1); in chameleon_parse_gdd()
55 mdev->rev = GDD_REV(reg1); in chameleon_parse_gdd()
56 mdev->var = GDD_VAR(reg1); in chameleon_parse_gdd()
88 mdev->irq.start = GDD_IRQ(reg1); in chameleon_parse_gdd()
89 mdev->irq.end = GDD_IRQ(reg1); in chameleon_parse_gdd()
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
A Dnv04.c185 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) in new_ramdac580() argument
187 bool head_a = (reg1 == 0x680508); in new_ramdac580()
198 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, in setPLL_double_highregs() argument
204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); in setPLL_double_highregs()
205 uint32_t oldpll1 = nvkm_rd32(device, reg1); in setPLL_double_highregs()
212 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); in setPLL_double_highregs()
220 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ in setPLL_double_highregs()
222 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); in setPLL_double_highregs()
246 switch (reg1) { in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/drivers/net/ethernet/netronome/nfp/bpf/
A Dverifier.c99 offmap = map_to_offmap(reg1->map_ptr); in nfp_bpf_map_update_value_ok()
203 bpf->helpers.map_lookup, reg1) || in nfp_bpf_check_helper_call()
211 bpf->helpers.map_update, reg1) || in nfp_bpf_check_helper_call()
261 reg1 = cur_regs(env) + BPF_REG_4; in nfp_bpf_check_helper_call()
264 reg1->type != PTR_TO_STACK && in nfp_bpf_check_helper_call()
266 reg1->type != PTR_TO_PACKET) { in nfp_bpf_check_helper_call()
268 reg1->type); in nfp_bpf_check_helper_call()
272 if (reg1->type == PTR_TO_STACK && in nfp_bpf_check_helper_call()
291 if (reg1->type != meta->arg1.type) { in nfp_bpf_check_helper_call()
293 meta->arg1.type, reg1->type); in nfp_bpf_check_helper_call()
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c76 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
77 .enable_reg = SRI(reg1, block, reg_num),\
79 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
81 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
82 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c121 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
122 .enable_reg = SRI(reg1, block, reg_num),\
123 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
125 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
126 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/misc/cardreader/
A Drtl8411.c41 u32 reg1 = 0; in rtl8411_fetch_vendor_settings() local
44 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg1); in rtl8411_fetch_vendor_settings()
45 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); in rtl8411_fetch_vendor_settings()
47 if (!rtsx_vendor_setting_valid(reg1)) in rtl8411_fetch_vendor_settings()
50 pcr->aspm_en = rtsx_reg_to_aspm(reg1); in rtl8411_fetch_vendor_settings()
52 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); in rtl8411_fetch_vendor_settings()
54 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); in rtl8411_fetch_vendor_settings()
/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
126 .enable_reg = SRI(reg1, block, reg_num),\
128 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
130 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
131 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
A Dirq_service_dcn10.c173 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
174 .enable_reg = SRI(reg1, block, reg_num),\
176 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
178 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
179 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

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