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Searched refs:reg2 (Results 1 – 25 of 80) sorted by relevance

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/drivers/rtc/
A Drtc-aspeed.c25 u32 reg1, reg2; in aspeed_rtc_read_time() local
33 reg2 = readl(rtc->base + RTC_YEAR); in aspeed_rtc_read_time()
35 } while (reg2 != readl(rtc->base + RTC_YEAR)); in aspeed_rtc_read_time()
42 cent = (reg2 >> 16) & 0x1f; in aspeed_rtc_read_time()
43 year = (reg2 >> 8) & 0x7f; in aspeed_rtc_read_time()
44 tm->tm_mon = ((reg2 >> 0) & 0x0f) - 1; in aspeed_rtc_read_time()
55 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
64 reg2 = ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) | in aspeed_rtc_set_time()
71 writel(reg2, rtc->base + RTC_YEAR); in aspeed_rtc_set_time()
/drivers/gpu/drm/i915/display/
A Dintel_pmdemand.c404 u32 reg1, reg2; in intel_pmdemand_init_pmdemand_params() local
431 REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
433 REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
445 REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
519 u32 *reg1, u32 *reg2, bool serialized) in intel_pmdemand_update_params() argument
556 update_reg(reg2, ddiclk_max, XELPDP_PMDEMAND_DDICLK_FREQ_MASK); in intel_pmdemand_update_params()
557 update_reg(reg2, plls, XELPDP_PMDEMAND_PLLS_MASK); in intel_pmdemand_update_params()
565 update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK); in intel_pmdemand_update_params()
579 u32 reg2, mod_reg2; in intel_pmdemand_program_params() local
590 mod_reg2 = reg2; in intel_pmdemand_program_params()
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/drivers/media/dvb-frontends/
A Dtua6100.c65 u8 reg2[] = { 0x02, 0x00, 0x00 }; in tua6100_set_params() local
68 struct i2c_msg msg2 = { .addr = priv->i2c_address, .flags = 0, .buf = reg2, .len = 3 }; in tua6100_set_params()
92 reg2[1] = (_R_VAL >> 8) & 0x03; in tua6100_set_params()
93 reg2[2] = _R_VAL; in tua6100_set_params()
95 reg2[1] |= 0x1c; in tua6100_set_params()
97 reg2[1] |= 0x0c; in tua6100_set_params()
99 reg2[1] |= 0x1c; in tua6100_set_params()
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 .ack_reg = SRI(reg2, block, reg_num),\
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
208 .ack_reg = SRI_DMUB(reg2),\
210 reg2 ## __ ## mask2 ## _MASK,\
212 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 .ack_reg = SRI(reg2, block, reg_num),\
191 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
195 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
203 .ack_reg = SRI_DMUB(reg2),\
205 reg2 ## __ ## mask2 ## _MASK,\
207 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn314/
A Dirq_service_dcn314.c183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
191 .ack_reg = SRI(reg2, block, reg_num),\
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
195 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
197 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
205 .ack_reg = SRI_DMUB(reg2),\
207 reg2 ## __ ## mask2 ## _MASK,\
209 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn315/
A Dirq_service_dcn315.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 .ack_reg = SRI(reg2, block, reg_num),\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
210 .ack_reg = SRI_DMUB(reg2),\
212 reg2 ## __ ## mask2 ## _MASK,\
214 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
201 .ack_reg = SRI(reg2, block, reg_num),\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
215 .ack_reg = SRI_DMUB(reg2),\
217 reg2 ## __ ## mask2 ## _MASK,\
219 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
185 .ack_reg = SRI(reg2, block, reg_num),\
186 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
187 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
204 .ack_reg = SRI_DMUB(reg2),\
206 reg2 ## __ ## mask2 ## _MASK,\
208 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
167 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
169 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
171 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
181 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
183 reg2 ## __ ## mask2 ## _MASK,\
185 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn401/
A Dirq_service_dcn401.c172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
180 .ack_reg = SRI(reg2, block, reg_num),\
182 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
184 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
194 .ack_reg = SRI_DMUB(reg2),\
196 reg2 ## __ ## mask2 ## _MASK,\
198 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn32/
A Dirq_service_dcn32.c192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
200 .ack_reg = SRI(reg2, block, reg_num),\
202 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
206 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
214 .ack_reg = SRI_DMUB(reg2),\
216 reg2 ## __ ## mask2 ## _MASK,\
218 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
188 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
190 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
192 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
194 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
202 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
204 reg2 ## __ ## mask2 ## _MASK,\
206 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn36/
A Dirq_service_dcn36.c158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
166 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
168 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
170 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
180 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
182 reg2 ## __ ## mask2 ## _MASK,\
184 reg2 ## __ ## mask2 ## _MASK \
/drivers/mcb/
A Dmcb-parse.c43 __le32 reg2; in chameleon_parse_gdd() local
50 reg2 = readl(&gdd->reg2); in chameleon_parse_gdd()
57 mdev->bar = GDD_BAR(reg2); in chameleon_parse_gdd()
58 mdev->group = GDD_GRP(reg2); in chameleon_parse_gdd()
59 mdev->inst = GDD_INS(reg2); in chameleon_parse_gdd()
/drivers/media/tuners/
A Dtda827x.c279 msg.buf = reg2; in tda827xo_set_analog_params()
281 reg2[0] = 0x80; in tda827xo_set_analog_params()
282 reg2[1] = 0; in tda827xo_set_analog_params()
285 reg2[0] = 0x60; in tda827xo_set_analog_params()
286 reg2[1] = 0xbf; in tda827xo_set_analog_params()
289 reg2[0] = 0x30; in tda827xo_set_analog_params()
294 reg2[0] = 0x30; in tda827xo_set_analog_params()
299 reg2[0] = 0x30; in tda827xo_set_analog_params()
304 reg2[0] = 0x30; in tda827xo_set_analog_params()
308 reg2[0] = 0x60; in tda827xo_set_analog_params()
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/drivers/power/supply/
A Dwm831x_power.c260 int ret, reg1, reg2; in wm831x_config_battery() local
271 reg2 = 0; in wm831x_config_battery()
280 reg2 |= WM831X_CHG_OFF_MSK; in wm831x_config_battery()
286 pdata->trickle_ilim, &reg2, in wm831x_config_battery()
290 pdata->vsel, &reg2, in wm831x_config_battery()
294 pdata->fast_ilim, &reg2, in wm831x_config_battery()
302 pdata->timeout, &reg2, in wm831x_config_battery()
326 reg2); in wm831x_config_battery()
/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c76 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
84 .ack_reg = SRI(reg2, block, reg_num),\
86 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
88 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c121 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
128 .ack_reg = SRI(reg2, block, reg_num),\
129 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
130 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/hwmon/
A Dnct7904.c392 unsigned int reg1, reg2, reg3; in nct7904_read_temp() local
466 reg2 = TEMP_CH1_W_REG; in nct7904_read_temp()
471 reg2 = TEMP_CH1_WH_REG; in nct7904_read_temp()
476 reg2 = TEMP_CH1_C_REG; in nct7904_read_temp()
481 reg2 = TEMP_CH1_CH_REG; in nct7904_read_temp()
492 reg2 + channel * 8); in nct7904_read_temp()
576 reg2 = TEMP_CH1_W_REG; in nct7904_write_temp()
581 reg2 = TEMP_CH1_WH_REG; in nct7904_write_temp()
586 reg2 = TEMP_CH1_C_REG; in nct7904_write_temp()
591 reg2 = TEMP_CH1_CH_REG; in nct7904_write_temp()
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/drivers/net/ethernet/sunplus/
A Dspl2sw_mdio.c20 u32 reg, reg2; in spl2sw_mdio_access() local
31 reg2 = FIELD_PREP(MAC_CPU_PHY_WT_DATA, wdata) | FIELD_PREP(MAC_CPU_PHY_CMD, cmd) | in spl2sw_mdio_access()
39 writel(reg2, comm->l2sw_reg_base + L2SW_PHY_CNTL_REG0); in spl2sw_mdio_access()
/drivers/net/ethernet/netronome/nfp/bpf/
A Dverifier.c50 const struct bpf_reg_state *reg2) in nfp_record_adjust_head() argument
59 if (reg2->type != SCALAR_VALUE || !tnum_is_const(reg2->var_off)) in nfp_record_adjust_head()
61 imm = reg2->var_off.value; in nfp_record_adjust_head()
175 const struct bpf_reg_state *reg2 = cur_regs(env) + BPF_REG_2; in nfp_bpf_check_helper_call() local
191 nfp_record_adjust_head(bpf, nfp_prog, meta, reg2); in nfp_bpf_check_helper_call()
204 !nfp_bpf_stack_arg_ok("map_lookup", env, reg2, in nfp_bpf_check_helper_call()
212 !nfp_bpf_stack_arg_ok("map_update", env, reg2, in nfp_bpf_check_helper_call()
222 !nfp_bpf_stack_arg_ok("map_delete", env, reg2, in nfp_bpf_check_helper_call()
305 meta->arg2.reg = *reg2; in nfp_bpf_check_helper_call()
/drivers/devfreq/event/
A Drockchip-dfi.c700 u32 reg2, reg3; in rk3568_dfi_init() local
702 regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, &reg2); in rk3568_dfi_init()
706 dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); in rk3568_dfi_init()
718 dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; in rk3568_dfi_init()
729 u32 reg2, reg3, reg4; in rk3588_dfi_init() local
731 regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, &reg2); in rk3588_dfi_init()
736 dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); in rk3588_dfi_init()
745 dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; in rk3588_dfi_init()
746 dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2; in rk3588_dfi_init()
749 dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) | in rk3588_dfi_init()
/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
133 .ack_reg = SRI(reg2, block, reg_num),\
135 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
137 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
A Dirq_service_dcn10.c173 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
181 .ack_reg = SRI(reg2, block, reg_num),\
183 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
185 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

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