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Searched refs:regHDP_CLK_CNTL (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dhdp_v5_2.c65 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
73 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
136 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
147 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
167 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_medium_grain_clock_gating()
176 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_get_clockgating_state()
A Dhdp_v7_0.c41 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); in hdp_v7_0_update_clock_gating()
48 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
110 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
A Dhdp_v6_0.c47 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v6_0_update_clock_gating()
57 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
122 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/hdp/
A Dhdp_6_0_0_offset.h66 #define regHDP_CLK_CNTL … macro
A Dhdp_4_4_2_offset.h72 #define regHDP_CLK_CNTL … macro
A Dhdp_7_0_0_offset.h66 #define regHDP_CLK_CNTL … macro
A Dhdp_5_2_1_offset.h70 #define regHDP_CLK_CNTL … macro

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