Searched refs:regHDP_MEM_POWER_CTRL (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | hdp_v7_0.c | 42 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_update_clock_gating()
67 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
103 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
119 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_get_clockgating_state()
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| A D | hdp_v6_0.c | 48 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_update_clock_gating()
76 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
112 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
131 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_get_clockgating_state()
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| A D | hdp_v5_2.c | 66 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_update_mem_power_gating()
92 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
127 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
186 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_get_clockgating_state()
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| /drivers/gpu/drm/amd/include/asic_reg/hdp/ |
| A D | hdp_6_0_0_offset.h | 60 #define regHDP_MEM_POWER_CTRL … macro
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| A D | hdp_4_4_2_offset.h | 64 #define regHDP_MEM_POWER_CTRL … macro
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| A D | hdp_7_0_0_offset.h | 64 #define regHDP_MEM_POWER_CTRL … macro
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| A D | hdp_5_2_1_offset.h | 64 #define regHDP_MEM_POWER_CTRL … macro
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