Searched refs:regIH_MEM_POWER_CTRL (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | ih_v6_0.c | 716 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL); in ih_v6_0_update_ih_mem_power_gating()
719 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); in ih_v6_0_update_ih_mem_power_gating()
760 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); in ih_v6_0_update_ih_mem_power_gating()
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| A D | ih_v6_1.c | 693 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL); in ih_v6_1_update_ih_mem_power_gating()
696 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); in ih_v6_1_update_ih_mem_power_gating()
737 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); in ih_v6_1_update_ih_mem_power_gating()
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| A D | ih_v7_0.c | 683 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL); in ih_v7_0_update_ih_mem_power_gating()
686 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); in ih_v7_0_update_ih_mem_power_gating()
727 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); in ih_v7_0_update_ih_mem_power_gating()
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| /drivers/gpu/drm/amd/include/asic_reg/oss/ |
| A D | osssys_4_4_2_offset.h | 214 #define regIH_MEM_POWER_CTRL … macro
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| A D | osssys_6_0_0_offset.h | 212 #define regIH_MEM_POWER_CTRL … macro
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| A D | osssys_6_1_0_offset.h | 156 #define regIH_MEM_POWER_CTRL … macro
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| A D | osssys_7_0_0_offset.h | 156 #define regIH_MEM_POWER_CTRL … macro
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