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Searched refs:reg_base (Results 1 – 25 of 400) sorted by relevance

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/drivers/gpu/drm/bridge/analogix/
A Danalogix_dp_reg.c241 reg = readl(dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
246 writel(reg, dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
267 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
272 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
276 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
282 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
286 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
292 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
296 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
302 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
[all …]
/drivers/gpio/
A Dgpio-bcm-kona.c162 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set()
188 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get()
226 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_input()
248 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_output()
283 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set_debounce()
358 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_ack()
377 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_mask()
397 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_unmask()
416 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_set_type()
464 reg_base = bank->kona_gpio->reg_base; in bcm_kona_gpio_irq_handler()
[all …]
A Dgpio-amdpt.c28 void __iomem *reg_base; member
41 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
64 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
66 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
89 if (IS_ERR(pt_gpio->reg_base)) { in pt_gpio_probe()
91 return PTR_ERR(pt_gpio->reg_base); in pt_gpio_probe()
95 pt_gpio->reg_base + PT_INPUTDATA_REG, in pt_gpio_probe()
96 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, in pt_gpio_probe()
97 pt_gpio->reg_base + PT_DIRECTION_REG, NULL, in pt_gpio_probe()
118 writel(0, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_probe()
[all …]
A Dgpio-loongson1.c21 void __iomem *reg_base; member
30 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset), in ls1x_gpio_request()
31 ls1x_gc->reg_base + GPIO_CFG); in ls1x_gpio_request()
43 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset), in ls1x_gpio_free()
44 ls1x_gc->reg_base + GPIO_CFG); in ls1x_gpio_free()
58 ls1x_gc->reg_base = devm_platform_ioremap_resource(pdev, 0); in ls1x_gpio_probe()
59 if (IS_ERR(ls1x_gc->reg_base)) in ls1x_gpio_probe()
60 return PTR_ERR(ls1x_gc->reg_base); in ls1x_gpio_probe()
62 ret = bgpio_init(&ls1x_gc->gc, dev, 4, ls1x_gc->reg_base + GPIO_DATA, in ls1x_gpio_probe()
63 ls1x_gc->reg_base + GPIO_OUTPUT, NULL, in ls1x_gpio_probe()
[all …]
A Dgpio-loongson-64bit.c35 void __iomem *reg_base; member
139 void __iomem *reg_base) in loongson_gpio_init() argument
143 lgpio->reg_base = reg_base; in loongson_gpio_init()
146 lgpio->reg_base + lgpio->chip_data->in_offset, in loongson_gpio_init()
147 lgpio->reg_base + lgpio->chip_data->out_offset, in loongson_gpio_init()
149 lgpio->reg_base + lgpio->chip_data->conf_offset, in loongson_gpio_init()
175 void __iomem *reg_base; in loongson_gpio_probe() local
185 reg_base = devm_platform_ioremap_resource(pdev, 0); in loongson_gpio_probe()
186 if (IS_ERR(reg_base)) in loongson_gpio_probe()
187 return PTR_ERR(reg_base); in loongson_gpio_probe()
[all …]
/drivers/media/platform/qcom/iris/
A Diris_vpu3x.c60 value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); in iris_vpu3x_hw_power_collapsed()
76 value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); in iris_vpu3_power_off_hardware()
94 writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); in iris_vpu3_power_off_hardware()
102 core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu3_power_off_hardware()
104 writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu3_power_off_hardware()
120 value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); in iris_vpu33_power_off_hardware()
140 core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu33_power_off_hardware()
172 core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); in iris_vpu33_power_off_controller()
196 val = readl(core->reg_base + AON_WRAPPER_SPARE); in iris_vpu33_power_off_controller()
198 writel(val, core->reg_base + AON_WRAPPER_SPARE); in iris_vpu33_power_off_controller()
[all …]
A Diris_vpu_common.c93 writel(value, core->reg_base + UC_REGION_ADDR); in iris_vpu_setup_ucregion_memory_map()
97 writel(value, core->reg_base + UC_REGION_SIZE); in iris_vpu_setup_ucregion_memory_map()
100 writel(value, core->reg_base + QTBL_ADDR); in iris_vpu_setup_ucregion_memory_map()
102 writel(QTBL_ENABLE, core->reg_base + QTBL_INFO); in iris_vpu_setup_ucregion_memory_map()
106 writel(value, core->reg_base + SFR_ADDR); in iris_vpu_setup_ucregion_memory_map()
116 writel(ctrl_init, core->reg_base + CTRL_INIT); in iris_vpu_boot_firmware()
117 writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); in iris_vpu_boot_firmware()
120 ctrl_status = readl(core->reg_base + CTRL_STATUS); in iris_vpu_boot_firmware()
136 writel(0x0, core->reg_base + CPU_CS_X2RPMH); in iris_vpu_boot_firmware()
177 ctrl_status = readl(core->reg_base + CTRL_STATUS); in iris_vpu_prepare_pc()
[all …]
/drivers/spi/
A Dspi-gxp.c43 void __iomem *reg_base; member
53 void __iomem *reg_base = spifi->reg_base; in gxp_spi_set_mode() local
58 writeb(0x55, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode()
59 writeb(0xaa, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode()
71 void __iomem *reg_base = spifi->reg_base; in gxp_spi_read_reg() local
81 writel(0, reg_base + OFFSET_SPIADDR); in gxp_spi_read_reg()
109 void __iomem *reg_base = spifi->reg_base; in gxp_spi_write_reg() local
119 writel(0, reg_base + OFFSET_SPIADDR); in gxp_spi_write_reg()
158 void __iomem *reg_base = spifi->reg_base; in gxp_spi_write() local
271 if (IS_ERR(spifi->reg_base)) in gxp_spifi_probe()
[all …]
A Dspi-fsl-spi.c93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
94 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
238 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
255 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
260 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
389 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
427 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_irq() local
462 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_irq() local
482 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control() local
497 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe() local
[all …]
A Dspi-cadence-quadspi.c449 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd() local
476 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext() local
498 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr() local
533 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read() local
616 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write() local
685 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup() local
716 reg = readl(reg_base + CQSPI_REG_SIZE); in cqspi_read_setup()
719 writel(reg, reg_base + CQSPI_REG_SIZE); in cqspi_read_setup()
730 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute() local
861 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable() local
[all …]
/drivers/irqchip/
A Dirq-csky-apb-intc.c34 static void __iomem *reg_base; variable
65 gc->reg_base = reg_base; in ck_set_gc()
110 reg_base = of_iomap(node, 0); in ck_intc_init_comm()
111 if (!reg_base) { in ck_intc_init_comm()
152 readl(reg_base + GX_INTC_PEN63_32), 32); in gx_irq_handler()
157 readl(reg_base + GX_INTC_PEN31_00), 0); in gx_irq_handler()
174 writel(0x0, reg_base + GX_INTC_NEN31_00); in gx_intc_init()
175 writel(0x0, reg_base + GX_INTC_NEN63_32); in gx_intc_init()
239 writel(0, reg_base + CK_INTC_NEN31_00); in ck_intc_init()
240 writel(0, reg_base + CK_INTC_NEN63_32); in ck_intc_init()
[all …]
/drivers/net/ethernet/cavium/thunder/
A Dthunder_xcv.c47 void __iomem *reg_base; member
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
95 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
127 cfg = readq_relaxed(xcv->reg_base + XCV_CTL); in xcv_setup_link()
130 writeq_relaxed(cfg, xcv->reg_base + XCV_CTL); in xcv_setup_link()
149 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_setup_link()
[all …]
/drivers/misc/mchp_pci1xxxx/
A Dmchp_pci1xxxx_gpio.c41 void __iomem *reg_base; member
72 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
76 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
127 data = readl(priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
132 writel(data, priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
361 pci1xxx_assign_bit(priv->reg_base, in pci1xxxx_gpio_suspend()
363 writel(~wake_mask, priv->reg_base + in pci1xxxx_gpio_suspend()
402 writel(wake_mask, priv->reg_base + in pci1xxxx_gpio_resume()
404 pci1xxx_assign_bit(priv->reg_base, in pci1xxxx_gpio_resume()
406 writel(0xffffffff, priv->reg_base + in pci1xxxx_gpio_resume()
[all …]
/drivers/ata/
A Dahci_qoriq.c61 struct ccsr_ahci *reg_base; member
167 void __iomem *reg_base = hpriv->mmio; in ahci_qoriq_phy_init() local
176 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
177 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
178 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
179 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
183 reg_base + LS1021A_AXICC_ADDR); in ahci_qoriq_phy_init()
194 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
195 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
203 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
[all …]
A Dahci_sunxi.c92 writel(0, reg_base + AHCI_RWCR); in ahci_sunxi_phy_init()
95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
96 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, in ahci_sunxi_phy_init()
102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); in ahci_sunxi_phy_init()
103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
106 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, in ahci_sunxi_phy_init()
110 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in ahci_sunxi_phy_init()
125 sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); in ahci_sunxi_phy_init()
[all …]
/drivers/remoteproc/
A Dmtk_scp.c175 val = readl(scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
177 writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
184 val = readl(scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
186 writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
221 scp->cluster->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
238 scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR); in mt8192_scp_irq_handler()
241 writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ); in mt8192_scp_irq_handler()
427 scp->cluster->reg_base + MT8183_SCP_CACHE_CON); in mt8183_scp_before_load()
474 scp->cluster->reg_base + MT8183_SCP_CACHE_CON); in mt8186_scp_before_load()
807 writel(0, scp->cluster->reg_base + MT8183_WDT_CFG); in mt8183_scp_stop()
[all …]
A Dqcom_q6v5_wcss.c110 void __iomem *reg_base; member
162 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
164 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
167 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
169 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
345 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
347 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
422 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
424 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
546 wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_qcs404_wcss_shutdown()
[all …]
/drivers/net/ethernet/marvell/octeontx2/af/
A Dptp.c160 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
164 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
174 return readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_nsec()
259 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_update()
261 ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_atomic_update()
269 regval = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_update()
272 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_update()
354 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_adjfine()
391 writeq(0, ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_start()
438 *clk = readq(ptp->reg_base + PTP_TIMESTAMP); in ptp_get_tstmp()
[all …]
/drivers/video/fbdev/mmp/hw/
A Dmmp_spi.c34 void __iomem *reg_base = (void __iomem *) in lcd_spi_write() local
55 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
58 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
60 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
63 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
71 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
74 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
83 void __iomem *reg_base = (void __iomem *) in lcd_spi_setup() local
91 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_setup()
102 reg_base + SPU_IOPAD_CONTROL); in lcd_spi_setup()
[all …]
/drivers/clk/samsung/
A Dclk-s5pv210-audss.c25 static void __iomem *reg_base; variable
74 if (IS_ERR(reg_base)) in s5pv210_audss_clk_probe()
75 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
117 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
139 reg_base + ASS_CLK_GATE, 6, 0, &lock); in s5pv210_audss_clk_probe()
145 reg_base + ASS_CLK_GATE, 5, 0, &lock); in s5pv210_audss_clk_probe()
148 reg_base + ASS_CLK_GATE, 4, 0, &lock); in s5pv210_audss_clk_probe()
151 reg_base + ASS_CLK_GATE, 3, 0, &lock); in s5pv210_audss_clk_probe()
154 reg_base + ASS_CLK_GATE, 2, 0, &lock); in s5pv210_audss_clk_probe()
157 reg_base + ASS_CLK_GATE, 1, 0, &lock); in s5pv210_audss_clk_probe()
[all …]
A Dclk-exynos-audss.c22 static void __iomem *reg_base; variable
140 if (IS_ERR(reg_base)) in exynos_audss_clk_probe()
141 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
187 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
198 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
214 reg_base + ASS_CLK_GATE, 0, 0, &lock); in exynos_audss_clk_probe()
218 reg_base + ASS_CLK_GATE, 2, 0, &lock); in exynos_audss_clk_probe()
222 reg_base + ASS_CLK_GATE, 3, 0, &lock); in exynos_audss_clk_probe()
226 reg_base + ASS_CLK_GATE, 4, 0, &lock); in exynos_audss_clk_probe()
233 reg_base + ASS_CLK_GATE, 5, 0, &lock); in exynos_audss_clk_probe()
[all …]
/drivers/rtc/
A Drtc-zynqmp.c52 void __iomem *reg_base; member
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
135 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
173 rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); in xlnx_init_rtc()
175 writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); in xlnx_init_rtc()
263 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_interrupt()
296 if (IS_ERR(xrtcdev->reg_base)) in xlnx_rtc_probe()
297 return PTR_ERR(xrtcdev->reg_base); in xlnx_rtc_probe()
[all …]
/drivers/input/serio/
A Dsun4i-ps2.c85 void __iomem *reg_base; member
118 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
125 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
151 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
158 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
172 writel(rval, drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_open()
183 rval = readl(drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_close()
230 if (!drvdata->reg_base) { in sun4i_ps2_probe()
259 writel(0, drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_probe()
289 iounmap(drvdata->reg_base); in sun4i_ps2_probe()
[all …]
/drivers/crypto/marvell/octeontx2/
A Dotx2_cptpf_main.c26 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
28 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
33 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
40 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
52 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
54 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
57 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
168 otx2_cpt_write64(pf->reg_base, BLKADDR_RVUM, 0, in cptpf_flr_wq_handler()
170 otx2_cpt_write64(pf->reg_base, BLKADDR_RVUM, 0, in cptpf_flr_wq_handler()
646 cptpf->reg_base, &cptpf->afpf_mbox, in cptpf_device_init()
[all …]
/drivers/clk/rockchip/
A Dclk-pll.c34 void __iomem *reg_base; member
220 pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_set_params()
228 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_set_params()
275 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_enable()
287 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_disable()
450 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
457 pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_set_params()
468 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
510 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_enable()
522 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_disable()
[all …]

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