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Searched refs:reg_bit (Results 1 – 8 of 8) sorted by relevance

/drivers/net/ipa/
A Dipa_main.c226 val &= ~reg_bit(reg, PA_MASK_EN); in ipa_hardware_config_tx()
247 val = reg_bit(reg, CLKON_MISC); in ipa_hardware_config_clkon()
250 val = reg_bit(reg, CLKON_GLOBAL); in ipa_hardware_config_clkon()
251 val |= reg_bit(reg, GLOBAL_2X_CLK); in ipa_hardware_config_clkon()
274 val &= ~reg_bit(reg, IPA_QMB_SELECT_CONS_EN); in ipa_hardware_config_comp()
275 val &= ~reg_bit(reg, IPA_QMB_SELECT_PROD_EN); in ipa_hardware_config_comp()
283 val |= reg_bit(reg, GSI_MULTI_INORDER_RD_DIS); in ipa_hardware_config_comp()
284 val |= reg_bit(reg, GSI_MULTI_INORDER_WR_DIS); in ipa_hardware_config_comp()
374 val |= reg_bit(reg, DPL_TIMESTAMP_SEL); in ipa_qtime_config()
404 val |= reg_bit(reg, DIV_ENABLE); in ipa_qtime_config()
[all …]
A Dipa_table.c367 val = reg_bit(reg, IPV6_ROUTER_HASH); in ipa_table_hash_flush()
368 val |= reg_bit(reg, IPV6_FILTER_HASH); in ipa_table_hash_flush()
369 val |= reg_bit(reg, IPV4_ROUTER_HASH); in ipa_table_hash_flush()
370 val |= reg_bit(reg, IPV4_FILTER_HASH); in ipa_table_hash_flush()
375 val = reg_bit(reg, ROUTER_CACHE); in ipa_table_hash_flush()
376 val |= reg_bit(reg, FILTER_CACHE); in ipa_table_hash_flush()
A Dipa_endpoint.c470 mask = reg_bit(reg, field_id); in ipa_endpoint_init_ctrl()
814 val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID); in ipa_endpoint_init_hdr()
818 val |= reg_bit(reg, HDR_OFST_METADATA_VALID); in ipa_endpoint_init_hdr()
840 val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */ in ipa_endpoint_init_hdr_ext()
850 val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID); in ipa_endpoint_init_hdr_ext()
852 val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING); in ipa_endpoint_init_hdr_ext()
1025 val |= reg_bit(reg, SW_EOF_ACTIVE); in ipa_endpoint_init_aggr()
1136 val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0; in ipa_endpoint_init_hol_block_en()
1281 val |= reg_bit(reg, STATUS_EN); in ipa_endpoint_status()
1647 val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE); in ipa_endpoint_default_route_set()
[all …]
A Dreg.h83 static inline u32 reg_bit(const struct reg *reg, u32 field_id) in reg_bit() function
A Dgsi.c727 val |= reg_bit(reg, EV_INTYPE); in gsi_evt_ring_program()
840 val |= reg_bit(reg, CHTYPE_DIR); in gsi_channel_program()
875 val |= reg_bit(reg, USE_DB_ENG); in gsi_channel_program()
883 val |= reg_bit(reg, USE_ESCAPE_BUF_ONLY); in gsi_channel_program()
889 val |= reg_bit(reg, DB_IN_BYTES); in gsi_channel_program()
1970 iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg)); in gsi_irq_setup()
2074 if (!(val & reg_bit(reg, ENABLED))) { in gsi_setup()
A Dipa_uc.c247 val = reg_bit(reg, UC_INTR); in send_uc_command()
/drivers/perf/arm_cspmu/
A Darm_cspmu.c718 u32 reg_id, reg_bit, inten_off, cnten_off; in arm_cspmu_enable_counter() local
721 reg_bit = COUNTER_TO_SET_CLR_BIT(idx); in arm_cspmu_enable_counter()
726 writel(BIT(reg_bit), cspmu->base0 + inten_off); in arm_cspmu_enable_counter()
727 writel(BIT(reg_bit), cspmu->base0 + cnten_off); in arm_cspmu_enable_counter()
732 u32 reg_id, reg_bit, inten_off, cnten_off; in arm_cspmu_disable_counter() local
735 reg_bit = COUNTER_TO_SET_CLR_BIT(idx); in arm_cspmu_disable_counter()
740 writel(BIT(reg_bit), cspmu->base0 + cnten_off); in arm_cspmu_disable_counter()
741 writel(BIT(reg_bit), cspmu->base0 + inten_off); in arm_cspmu_disable_counter()
/drivers/net/ethernet/hisilicon/hns3/hns3pf/
A Dhclge_main.c3837 u32 val, reg, reg_bit; in hclge_reset_wait() local
3843 reg_bit = HCLGE_IMP_RESET_BIT; in hclge_reset_wait()
3847 reg_bit = HCLGE_GLOBAL_RESET_BIT; in hclge_reset_wait()
3851 reg_bit = HCLGE_FUN_RST_ING_B; in hclge_reset_wait()
3861 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { in hclge_reset_wait()

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