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Searched refs:reg_cfg (Results 1 – 25 of 26) sorted by relevance

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/drivers/clk/mediatek/
A Dclk-fhctl.c73 writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
74 writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
75 writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
79 r = readl(regs->reg_cfg); in fhctl_set_ssc_regs()
82 writel(r, regs->reg_cfg); in fhctl_set_ssc_regs()
84 r = readl(regs->reg_cfg); in fhctl_set_ssc_regs()
87 writel(r, regs->reg_cfg); in fhctl_set_ssc_regs()
101 writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg); in fhctl_set_ssc_regs()
103 writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg); in fhctl_set_ssc_regs()
131 writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg); in hopping_hw_flow()
[all …]
A Dclk-pllfh.h50 void __iomem *reg_cfg; member
A Dclk-pllfh.c132 regs->reg_cfg = fhx_base + offset->offset_cfg; in pllfh_init()
/drivers/gpu/drm/imx/dc/
A Ddc-fu.c98 regmap_write_bits(fu->reg_cfg, STATICCONTROL, SHDEN, SHDEN); in dc_fu_enable_shden()
103 regmap_write_bits(fu->reg_cfg, STATICCONTROL, in dc_fu_baddr_autoupdate()
122 regmap_write_bits(fu->reg_cfg, BURSTBUFFERMANAGEMENT, in dc_fu_set_numbuffers()
135 regmap_write_bits(fu->reg_cfg, BURSTBUFFERMANAGEMENT, in dc_fu_set_burstlength()
142 regmap_write(fu->reg_cfg, fu->reg_baseaddr[frac], baddr); in dc_fu_set_baseaddress()
168 regmap_write(fu->reg_cfg, fu->reg_layeroffset[frac], in dc_fu_layeroffset()
175 regmap_write(fu->reg_cfg, fu->reg_clipwindowoffset[frac], in dc_fu_clipoffset()
189 regmap_write(fu->reg_cfg, fu->reg_layerproperty[frac], 0); in dc_fu_set_pixel_blend_mode()
190 regmap_write(fu->reg_cfg, fu->reg_constantcolor[frac], 0); in dc_fu_set_pixel_blend_mode()
195 regmap_write_bits(fu->reg_cfg, fu->reg_layerproperty[frac], in dc_fu_enable_src_buf()
[all …]
A Ddc-cf.c56 regmap_write(cf->reg_cfg, STATICCONTROL, SHDEN); in dc_cf_enable_shden()
67 regmap_write(cf->reg_cfg, FRAMEDIMENSIONS, WIDTH(w) | HEIGHT(h)); in dc_cf_framedimensions()
72 regmap_write(cf->reg_cfg, CONSTANTCOLOR, 0); in dc_cf_constantcolor_black()
77 regmap_write(cf->reg_cfg, CONSTANTCOLOR, BLUE(0xff)); in dc_cf_constantcolor_blue()
104 cf->reg_cfg = devm_regmap_init_mmio(dev, base_cfg, in dc_cf_bind()
106 if (IS_ERR(cf->reg_cfg)) in dc_cf_bind()
107 return PTR_ERR(cf->reg_cfg); in dc_cf_bind()
A Ddc-fw.c88 regmap_write_bits(fu->reg_cfg, CONTROL, INPUTSELECT_MASK, in dc_fw_set_fmt()
90 regmap_write_bits(fu->reg_cfg, CONTROL, RASTERMODE_MASK, in dc_fw_set_fmt()
93 regmap_write_bits(fu->reg_cfg, LAYERPROPERTY(frac), in dc_fw_set_fmt()
100 regmap_write(fu->reg_cfg, COLORCOMPONENTBITS(frac), bits); in dc_fw_set_fmt()
101 regmap_write(fu->reg_cfg, COLORCOMPONENTSHIFT(frac), shifts); in dc_fw_set_fmt()
106 regmap_write(fu->reg_cfg, FRAMEDIMENSIONS, in dc_fw_set_framedimensions()
155 fu->reg_cfg = devm_regmap_init_mmio(dev, base_cfg, in dc_fw_bind()
157 if (IS_ERR(fu->reg_cfg)) in dc_fw_bind()
158 return PTR_ERR(fu->reg_cfg); in dc_fw_bind()
A Ddc-lb.c193 regmap_write_bits(lb->reg_cfg, STATICCONTROL, SHDEN, SHDEN); in dc_lb_enable_shden()
198 regmap_write_bits(lb->reg_cfg, STATICCONTROL, SHDTOKSEL_MASK, in dc_lb_shdtoksel()
204 regmap_write_bits(lb->reg_cfg, STATICCONTROL, SHDLDSEL_MASK, in dc_lb_shdldsel()
210 regmap_write_bits(lb->reg_cfg, CONTROL, CTRL_MODE_MASK, mode); in dc_lb_mode()
221 regmap_write(lb->reg_cfg, BLENDCONTROL, val); in dc_lb_blendcontrol()
226 regmap_write(lb->reg_cfg, POSITION, XPOS(x) | YPOS(y)); in dc_lb_position()
271 lb->reg_cfg = devm_regmap_init_mmio(dev, base_cfg, in dc_lb_bind()
273 if (IS_ERR(lb->reg_cfg)) in dc_lb_bind()
274 return PTR_ERR(lb->reg_cfg); in dc_lb_bind()
A Ddc-fl.c65 regmap_write_bits(fu->reg_cfg, LAYERPROPERTY(frac), in dc_fl_set_fmt()
72 regmap_write(fu->reg_cfg, COLORCOMPONENTBITS(frac), bits); in dc_fl_set_fmt()
73 regmap_write(fu->reg_cfg, COLORCOMPONENTSHIFT(frac), shifts); in dc_fl_set_fmt()
78 regmap_write(fu->reg_cfg, FRAMEDIMENSIONS, in dc_fl_set_framedimensions()
118 fu->reg_cfg = devm_regmap_init_mmio(dev, base_cfg, in dc_fl_bind()
120 if (IS_ERR(fu->reg_cfg)) in dc_fl_bind()
121 return PTR_ERR(fu->reg_cfg); in dc_fl_bind()
A Ddc-ed.c160 regmap_write_bits(ed->reg_cfg, STATICCONTROL, SHDEN, SHDEN); in dc_ed_enable_shden()
165 regmap_write_bits(ed->reg_cfg, STATICCONTROL, KICK_MODE, EXTERNAL); in dc_ed_kick_mode_external()
170 regmap_write_bits(ed->reg_cfg, STATICCONTROL, PERFCOUNTMODE, 0); in dc_ed_disable_perfcountmode()
175 regmap_write_bits(ed->reg_cfg, CONTROL, GAMMAAPPLYENABLE, 0); in dc_ed_disable_gamma_apply()
218 ed->reg_cfg = devm_regmap_init_mmio(dev, base_cfg, in dc_ed_bind()
220 if (IS_ERR(ed->reg_cfg)) in dc_ed_bind()
221 return PTR_ERR(ed->reg_cfg); in dc_ed_bind()
A Ddc-pe.h49 struct regmap *reg_cfg; member
56 struct regmap *reg_cfg; member
63 struct regmap *reg_cfg; member
A Ddc-fu.h103 struct regmap *reg_cfg; member
/drivers/gpu/drm/bridge/
A Dlontium-lt9611.c96 const struct reg_sequence reg_cfg[] = { in lt9611_mipi_input_analog() local
108 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
114 struct reg_sequence reg_cfg[] = { in lt9611_mipi_input_digital() local
124 reg_cfg[1].def = 0x03; in lt9611_mipi_input_digital()
126 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_digital()
204 regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_pcr_setup()
241 regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_pll_setup()
348 struct reg_sequence reg_cfg[] = { in lt9611_hdmi_tx_phy() local
367 reg_cfg[2].def = 0x73; in lt9611_hdmi_tx_phy()
369 regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_hdmi_tx_phy()
[all …]
/drivers/dma/
A Dste_dma40_ll.c137 u32 reg_cfg, in d40_phy_fill_lli() argument
172 lli->reg_cfg = reg_cfg; in d40_phy_fill_lli()
182 lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS); in d40_phy_fill_lli()
184 lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS); in d40_phy_fill_lli()
214 dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg, in d40_phy_buf_to_lli() argument
250 reg_cfg, info, flags); in d40_phy_buf_to_lli()
271 u32 reg_cfg, in d40_phy_sg_to_lli() argument
299 reg_cfg, info, otherinfo, flags); in d40_phy_sg_to_lli()
364 u32 reg_cfg, in d40_log_fill_lli() argument
370 lli->lcsp13 = reg_cfg; in d40_log_fill_lli()
A Dste_dma40_ll.h345 u32 reg_cfg; member
446 u32 reg_cfg,
A Dste_dma40.c835 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); in d40_phy_lli_load()
840 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); in d40_phy_lli_load()
/drivers/regulator/
A Drt5759-regulator.c214 struct regulator_config reg_cfg; in rt5759_regulator_register() local
246 memset(&reg_cfg, 0, sizeof(reg_cfg)); in rt5759_regulator_register()
247 reg_cfg.dev = priv->dev; in rt5759_regulator_register()
248 reg_cfg.of_node = np; in rt5759_regulator_register()
249 reg_cfg.init_data = of_get_regulator_init_data(priv->dev, np, reg_desc); in rt5759_regulator_register()
250 reg_cfg.regmap = priv->regmap; in rt5759_regulator_register()
252 rdev = devm_regulator_register(priv->dev, reg_desc, &reg_cfg); in rt5759_regulator_register()
A Drtq6752-regulator.c222 struct regulator_config reg_cfg = {}; in rtq6752_probe() local
255 reg_cfg.dev = &i2c->dev; in rtq6752_probe()
256 reg_cfg.regmap = priv->regmap; in rtq6752_probe()
257 reg_cfg.driver_data = priv; in rtq6752_probe()
262 &reg_cfg); in rtq6752_probe()
/drivers/ata/
A Dpata_octeon_cf.c87 union cvmx_mio_boot_reg_cfgx reg_cfg; in octeon_cf_set_boot_reg_cfg() local
105 reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); in octeon_cf_set_boot_reg_cfg()
106 reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ in octeon_cf_set_boot_reg_cfg()
107 reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */ in octeon_cf_set_boot_reg_cfg()
108 reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ in octeon_cf_set_boot_reg_cfg()
110 reg_cfg.s.we_ext = 0; /* No write enable extension */ in octeon_cf_set_boot_reg_cfg()
111 reg_cfg.s.oe_ext = 0; /* No read enable extension */ in octeon_cf_set_boot_reg_cfg()
112 reg_cfg.s.en = 1; /* Enable this region */ in octeon_cf_set_boot_reg_cfg()
113 reg_cfg.s.orbit = 0; /* Don't combine with previous region */ in octeon_cf_set_boot_reg_cfg()
114 reg_cfg.s.ale = 0; /* Don't do address multiplexing */ in octeon_cf_set_boot_reg_cfg()
[all …]
/drivers/iommu/
A Dsprd-iommu.c214 unsigned int reg_cfg; in sprd_iommu_hw_en() local
218 reg_cfg = SPRD_EX_CFG; in sprd_iommu_hw_en()
220 reg_cfg = SPRD_VAU_CFG; in sprd_iommu_hw_en()
224 sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val); in sprd_iommu_hw_en()
/drivers/clk/sprd/
A Dpll.h13 struct reg_cfg { struct
A Dpll.c151 struct reg_cfg *cfg; in _sprd_pll_set_rate()
/drivers/net/wireless/realtek/rtw88/
A Dsdio.c155 u32 reg_cfg; in rtw_sdio_indirect_reg_cfg() local
159 reg_cfg = rtw_sdio_to_bus_offset(rtwdev, REG_SDIO_INDIRECT_REG_CFG); in rtw_sdio_indirect_reg_cfg()
162 reg_cfg, &ret); in rtw_sdio_indirect_reg_cfg()
167 tmp = sdio_readb(rtwsdio->sdio_func, reg_cfg + 2, &ret); in rtw_sdio_indirect_reg_cfg()
/drivers/net/wireless/marvell/mwifiex/
A Dsta_cmdresp.c1129 struct host_cmd_ds_chan_region_cfg *reg = &resp->params.reg_cfg; in mwifiex_ret_chan_region_cfg()
A Dfw.h2443 struct host_cmd_ds_chan_region_cfg reg_cfg; member
A Dsta_cmd.c1599 struct host_cmd_ds_chan_region_cfg *reg = &cmd->params.reg_cfg; in mwifiex_cmd_chan_region_cfg()

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