Searched refs:reg_entry (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/tegra/ |
| A D | rgb.c | 32 struct reg_entry { struct
37 static const struct reg_entry rgb_enable[] = { argument
59 static const struct reg_entry rgb_disable[] = {
82 const struct reg_entry *table, in tegra_dc_write_regs()
|
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_ras.c | 4879 const struct amdgpu_ras_err_status_reg_entry *reg_entry, in amdgpu_ras_inst_get_memory_id_field() argument
4885 if (!reg_entry) in amdgpu_ras_inst_get_memory_id_field()
4889 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_memory_id_field()
4890 reg_entry->seg_lo, reg_entry->reg_lo); in amdgpu_ras_inst_get_memory_id_field()
4893 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) && in amdgpu_ras_inst_get_memory_id_field()
4903 const struct amdgpu_ras_err_status_reg_entry *reg_entry, in amdgpu_ras_inst_get_err_cnt_field() argument
4909 if (!reg_entry) in amdgpu_ras_inst_get_err_cnt_field()
4913 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_err_cnt_field()
4914 reg_entry->seg_hi, reg_entry->reg_hi); in amdgpu_ras_inst_get_err_cnt_field()
4917 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) && in amdgpu_ras_inst_get_err_cnt_field()
|
| A D | amdgpu_ras.h | 924 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
928 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
|
| A D | gfx_v9_4_3.c | 4388 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { in gfx_v9_4_3_inst_query_ras_err_count()
4391 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_query_ras_err_count()
4395 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()
4404 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()
4421 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_query_ras_err_count()
4425 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()
4459 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_reset_ras_err_count()
4463 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), in gfx_v9_4_3_inst_reset_ras_err_count()
4468 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), in gfx_v9_4_3_inst_reset_ras_err_count()
4481 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_reset_ras_err_count()
[all …]
|
| A D | amdgpu_gfx.h | 537 struct amdgpu_ras_err_status_reg_entry reg_entry; member
|
Completed in 29 milliseconds