Searched refs:reg_layout (Results 1 – 13 of 13) sorted by relevance
| /drivers/soundwire/ |
| A D | qcom.c | 182 const unsigned int *reg_layout; member
221 const unsigned int *reg_layout; member
240 .reg_layout = swrm_v1_3_reg_layout,
247 .reg_layout = swrm_v1_3_reg_layout,
255 .reg_layout = swrm_v1_3_reg_layout,
275 .reg_layout = swrm_v2_0_reg_layout,
514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], in qcom_swrm_cmd_fifo_rd_cmd()
714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
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| /drivers/clk/renesas/ |
| A D | renesas-cpg-mssr.c | 184 enum clk_reg_layout reg_layout; member
258 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
294 priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) in cpg_mstp_clock_endisable()
323 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
365 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
973 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
1004 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
1101 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_reserved_init()
1159 priv->reg_layout = info->reg_layout; in cpg_mssr_common_init()
1265 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A || in cpg_mssr_probe()
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| A D | r7s9210-cpg-mssr.c | 216 .reg_layout = CLK_REG_LAYOUT_RZ_A,
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| A D | renesas-cpg-mssr.h | 164 enum clk_reg_layout reg_layout; member
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| A D | r8a779f0-cpg-mssr.c | 237 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
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| A D | r9a09g077-cpg.c | 254 .reg_layout = CLK_REG_LAYOUT_RZ_T2H,
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| A D | r8a779a0-cpg-mssr.c | 312 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
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| A D | r8a779g0-cpg-mssr.c | 310 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
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| A D | r8a779h0-cpg-mssr.c | 306 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
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| /drivers/tty/serial/8250/ |
| A D | 8250_dfl.c | 55 u64 fifo_len, clk_freq, reg_layout; in dfl_uart_get_params() local
86 ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, ®_layout); in dfl_uart_get_params()
90 uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); in dfl_uart_get_params()
91 reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); in dfl_uart_get_params()
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| /drivers/dma/ |
| A D | hisi_dma.c | 164 enum hisi_dma_reg_layout reg_layout; member
369 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_mask_irq()
385 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_unmask_irq()
638 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_init_hw_qp()
803 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_set_mode()
851 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs()
862 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs()
952 enum hisi_dma_reg_layout reg_layout; in hisi_dma_probe() local
960 reg_layout = hisi_dma_get_reg_layout(pdev); in hisi_dma_probe()
961 if (reg_layout == HISI_DMA_REG_LAYOUT_INVALID) { in hisi_dma_probe()
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| /drivers/clk/samsung/ |
| A D | clk.h | 294 enum exynos_cpuclk_layout reg_layout; member
306 .reg_layout = _layout, \
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| A D | clk-cpu.c | 679 cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout]; in exynos_register_cpu_clock()
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