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Searched refs:reg_num (Results 1 – 25 of 142) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c134 #define hpd_int_entry(reg_num)\ argument
136 IRQ_REG_ENTRY(HPD, reg_num,\
143 #define hpd_rx_int_entry(reg_num)\ argument
145 IRQ_REG_ENTRY(HPD, reg_num,\
151 #define pflip_int_entry(reg_num)\ argument
164 IRQ_REG_ENTRY(OTG, reg_num,\
170 #define vblank_int_entry(reg_num)\ argument
172 IRQ_REG_ENTRY(OTG, reg_num,\
178 #define vline0_int_entry(reg_num)\ argument
180 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c139 #define hpd_int_entry(reg_num)\ argument
141 IRQ_REG_ENTRY(HPD, reg_num,\
148 #define hpd_rx_int_entry(reg_num)\ argument
150 IRQ_REG_ENTRY(HPD, reg_num,\
156 #define pflip_int_entry(reg_num)\ argument
158 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
166 IRQ_REG_ENTRY(OTG, reg_num,\
177 IRQ_REG_ENTRY(OTG, reg_num,\
184 IRQ_REG_ENTRY(OTG, reg_num,\
192 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c90 #define hpd_int_entry(reg_num)\ argument
92 IRQ_REG_ENTRY(HPD, reg_num,\
99 #define hpd_rx_int_entry(reg_num)\ argument
101 IRQ_REG_ENTRY(HPD, reg_num,\
107 #define pflip_int_entry(reg_num)\ argument
109 IRQ_REG_ENTRY(DCP, reg_num, \
116 #define vupdate_int_entry(reg_num)\ argument
118 IRQ_REG_ENTRY(CRTC, reg_num,\
124 #define vblank_int_entry(reg_num)\ argument
126 IRQ_REG_ENTRY(CRTC, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c160 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
167 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
187 #define hpd_int_entry(reg_num)\ argument
192 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
194 #define hpd_rx_int_entry(reg_num)\ argument
198 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
201 #define pflip_int_entry(reg_num)\ argument
216 #define vblank_int_entry(reg_num)\ argument
222 #define vline0_int_entry(reg_num)\ argument
237 #define i2c_int_entry(reg_num) \ argument
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c181 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
188 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
208 #define hpd_int_entry(reg_num)\ argument
213 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
215 #define hpd_rx_int_entry(reg_num)\ argument
219 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
222 #define pflip_int_entry(reg_num)\ argument
237 #define vblank_int_entry(reg_num)\ argument
243 #define vline0_int_entry(reg_num)\ argument
258 #define i2c_int_entry(reg_num) \ argument
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn36/
A Dirq_service_dcn36.c159 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
166 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
186 #define hpd_int_entry(reg_num)\ argument
191 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
193 #define hpd_rx_int_entry(reg_num)\ argument
197 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
200 #define pflip_int_entry(reg_num)\ argument
215 #define vblank_int_entry(reg_num)\ argument
221 #define vline0_int_entry(reg_num)\ argument
236 #define i2c_int_entry(reg_num) \ argument
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/drivers/gpu/drm/amd/display/dc/irq/dce80/
A Dirq_service_dce80.c65 #define hpd_int_entry(reg_num)\ argument
66 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
80 #define hpd_rx_int_entry(reg_num)\ argument
81 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
94 #define pflip_int_entry(reg_num)\ argument
95 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
109 #define vupdate_int_entry(reg_num)\ argument
125 #define vblank_int_entry(reg_num)\ argument
147 #define i2c_int_entry(reg_num) \ argument
150 #define dp_sink_int_entry(reg_num) \ argument
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn401/
A Dirq_service_dcn401.c200 #define hpd_int_entry(reg_num)\ argument
202 IRQ_REG_ENTRY(HPD, reg_num,\
209 #define hpd_rx_int_entry(reg_num)\ argument
211 IRQ_REG_ENTRY(HPD, reg_num,\
217 #define pflip_int_entry(reg_num)\ argument
227 IRQ_REG_ENTRY(OTG, reg_num,\
237 IRQ_REG_ENTRY(OTG, reg_num,\
245 IRQ_REG_ENTRY(OTG, reg_num,\
252 IRQ_REG_ENTRY(OTG, reg_num,\
259 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn32/
A Dirq_service_dcn32.c220 #define hpd_int_entry(reg_num)\ argument
222 IRQ_REG_ENTRY(HPD, reg_num,\
229 #define hpd_rx_int_entry(reg_num)\ argument
231 IRQ_REG_ENTRY(HPD, reg_num,\
237 #define pflip_int_entry(reg_num)\ argument
247 IRQ_REG_ENTRY(OTG, reg_num,\
257 IRQ_REG_ENTRY(OTG, reg_num,\
265 IRQ_REG_ENTRY(OTG, reg_num,\
272 IRQ_REG_ENTRY(OTG, reg_num,\
279 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
A Dirq_service_dcn10.c187 #define hpd_int_entry(reg_num)\ argument
189 IRQ_REG_ENTRY(HPD, reg_num,\
196 #define hpd_rx_int_entry(reg_num)\ argument
198 IRQ_REG_ENTRY(HPD, reg_num,\
204 #define pflip_int_entry(reg_num)\ argument
206 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
217 IRQ_REG_ENTRY(OTG, reg_num,\
223 #define vblank_int_entry(reg_num)\ argument
225 IRQ_REG_ENTRY(OTG, reg_num,\
233 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn20/
A Dirq_service_dcn20.c192 #define hpd_int_entry(reg_num)\ argument
194 IRQ_REG_ENTRY(HPD, reg_num,\
201 #define hpd_rx_int_entry(reg_num)\ argument
203 IRQ_REG_ENTRY(HPD, reg_num,\
209 #define pflip_int_entry(reg_num)\ argument
211 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
222 IRQ_REG_ENTRY(OTG, reg_num,\
228 #define vblank_int_entry(reg_num)\ argument
230 IRQ_REG_ENTRY(OTG, reg_num,\
238 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce60/
A Dirq_service_dce60.c74 #define hpd_int_entry(reg_num)\ argument
75 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
89 #define hpd_rx_int_entry(reg_num)\ argument
90 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
103 #define pflip_int_entry(reg_num)\ argument
104 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
118 #define vupdate_int_entry(reg_num)\ argument
134 #define vblank_int_entry(reg_num)\ argument
155 #define i2c_int_entry(reg_num) \ argument
158 #define dp_sink_int_entry(reg_num) \ argument
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c214 #define hpd_int_entry(reg_num)\ argument
216 IRQ_REG_ENTRY(HPD, reg_num,\
223 #define hpd_rx_int_entry(reg_num)\ argument
225 IRQ_REG_ENTRY(HPD, reg_num,\
231 #define pflip_int_entry(reg_num)\ argument
233 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
244 IRQ_REG_ENTRY(OTG, reg_num,\
250 #define vblank_int_entry(reg_num)\ argument
252 IRQ_REG_ENTRY(OTG, reg_num,\
260 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c209 #define hpd_int_entry(reg_num)\ argument
211 IRQ_REG_ENTRY(HPD, reg_num,\
218 #define hpd_rx_int_entry(reg_num)\ argument
220 IRQ_REG_ENTRY(HPD, reg_num,\
226 #define pflip_int_entry(reg_num)\ argument
228 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
239 IRQ_REG_ENTRY(OTG, reg_num,\
245 #define vblank_int_entry(reg_num)\ argument
247 IRQ_REG_ENTRY(OTG, reg_num,\
255 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn314/
A Dirq_service_dcn314.c211 #define hpd_int_entry(reg_num)\ argument
213 IRQ_REG_ENTRY(HPD, reg_num,\
220 #define hpd_rx_int_entry(reg_num)\ argument
222 IRQ_REG_ENTRY(HPD, reg_num,\
228 #define pflip_int_entry(reg_num)\ argument
230 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
241 IRQ_REG_ENTRY(OTG, reg_num,\
247 #define vblank_int_entry(reg_num)\ argument
249 IRQ_REG_ENTRY(OTG, reg_num,\
257 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn315/
A Dirq_service_dcn315.c216 #define hpd_int_entry(reg_num)\ argument
218 IRQ_REG_ENTRY(HPD, reg_num,\
225 #define hpd_rx_int_entry(reg_num)\ argument
227 IRQ_REG_ENTRY(HPD, reg_num,\
233 #define pflip_int_entry(reg_num)\ argument
235 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
246 IRQ_REG_ENTRY(OTG, reg_num,\
252 #define vblank_int_entry(reg_num)\ argument
254 IRQ_REG_ENTRY(OTG, reg_num,\
262 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c221 #define hpd_int_entry(reg_num)\ argument
223 IRQ_REG_ENTRY(HPD, reg_num,\
230 #define hpd_rx_int_entry(reg_num)\ argument
232 IRQ_REG_ENTRY(HPD, reg_num,\
238 #define pflip_int_entry(reg_num)\ argument
240 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
251 IRQ_REG_ENTRY(OTG, reg_num,\
257 #define vblank_int_entry(reg_num)\ argument
259 IRQ_REG_ENTRY(OTG, reg_num,\
274 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c210 #define hpd_int_entry(reg_num)\ argument
212 IRQ_REG_ENTRY(HPD, reg_num,\
219 #define hpd_rx_int_entry(reg_num)\ argument
221 IRQ_REG_ENTRY(HPD, reg_num,\
227 #define pflip_int_entry(reg_num)\ argument
240 IRQ_REG_ENTRY(OTG, reg_num,\
246 #define vblank_int_entry(reg_num)\ argument
248 IRQ_REG_ENTRY(OTG, reg_num,\
254 #define vline0_int_entry(reg_num)\ argument
256 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce110/
A Dirq_service_dce110.c89 #define hpd_int_entry(reg_num)\ argument
90 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
104 #define hpd_rx_int_entry(reg_num)\ argument
105 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
117 #define pflip_int_entry(reg_num)\ argument
118 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
132 #define vupdate_int_entry(reg_num)\ argument
148 #define vblank_int_entry(reg_num)\ argument
170 #define i2c_int_entry(reg_num) \ argument
173 #define dp_sink_int_entry(reg_num) \ argument
[all …]
/drivers/video/fbdev/via/
A Dhw.h355 int reg_num; member
361 int reg_num; member
367 int reg_num; member
373 int reg_num; member
379 int reg_num; member
385 int reg_num; member
391 int reg_num; member
397 int reg_num; member
403 int reg_num; member
409 int reg_num; member
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/drivers/net/ethernet/hisilicon/hns3/hns3vf/
A Dhclgevf_regs.c130 int i, j, reg_num; in hclgevf_get_regs() local
137 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); in hclgevf_get_regs()
138 reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_CMDQ, reg_num, reg); in hclgevf_get_regs()
139 for (i = 0; i < reg_num; i++) in hclgevf_get_regs()
142 reg_num = ARRAY_SIZE(common_reg_addr_list); in hclgevf_get_regs()
144 for (i = 0; i < reg_num; i++) in hclgevf_get_regs()
147 reg_num = ARRAY_SIZE(ring_reg_addr_list); in hclgevf_get_regs()
151 for (i = 0; i < reg_num; i++) in hclgevf_get_regs()
157 reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); in hclgevf_get_regs()
160 reg_num, reg); in hclgevf_get_regs()
[all …]
/drivers/irqchip/
A Dirq-imx-irqsteer.c35 int reg_num; member
45 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index()
56 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
146 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler()
150 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler()
196 data->reg_num = irqs_num / 32; in imx_irqsteer_probe()
200 sizeof(u32) * data->reg_num, in imx_irqsteer_probe()
273 for (i = 0; i < data->reg_num; i++) in imx_irqsteer_save_regs()
275 CHANMASK(i, data->reg_num)); in imx_irqsteer_save_regs()
283 for (i = 0; i < data->reg_num; i++) in imx_irqsteer_restore_regs()
[all …]
/drivers/net/ethernet/hisilicon/hns3/hns3pf/
A Dhclge_regs.c378 reg_num = entries_per_desc * bd_num; in hclge_dfx_reg_fetch_data()
379 for (i = 0; i < reg_num; i++) { in hclge_dfx_reg_fetch_data()
385 return reg_num; in hclge_dfx_reg_fetch_data()
516 int i, j, reg_num; in hclge_fetch_pf_reg() local
521 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); in hclge_fetch_pf_reg()
523 for (i = 0; i < reg_num; i++) in hclge_fetch_pf_reg()
527 reg_num = ARRAY_SIZE(common_reg_addr_list); in hclge_fetch_pf_reg()
529 for (i = 0; i < reg_num; i++) in hclge_fetch_pf_reg()
533 reg_num = ARRAY_SIZE(ring_reg_addr_list); in hclge_fetch_pf_reg()
537 for (i = 0; i < reg_num; i++) in hclge_fetch_pf_reg()
[all …]
/drivers/input/keyboard/
A Dbcm-keypad.c93 static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode) in bcm_kp_report_keys() argument
102 writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); in bcm_kp_report_keys()
104 state = readl(kp->base + KPSSRN_OFFSET(reg_num)); in bcm_kp_report_keys()
105 change = kp->last_state[reg_num] ^ state; in bcm_kp_report_keys()
106 kp->last_state[reg_num] = state; in bcm_kp_report_keys()
112 row = BIT_TO_ROW_SSRN(bit_nr, reg_num); in bcm_kp_report_keys()
123 int reg_num; in bcm_kp_isr_thread() local
125 for (reg_num = 0; reg_num <= 1; reg_num++) in bcm_kp_isr_thread()
126 bcm_kp_report_keys(kp, reg_num, pull_mode); in bcm_kp_isr_thread()
/drivers/net/ethernet/arc/
A Demac_mdio.c56 static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) in arc_mdio_read() argument
63 0x60020000 | (phy_addr << 23) | (reg_num << 18)); in arc_mdio_read()
72 phy_addr, reg_num, value); in arc_mdio_read()
89 int reg_num, u16 value) in arc_mdio_write() argument
95 phy_addr, reg_num, value); in arc_mdio_write()
98 0x50020000 | (phy_addr << 23) | (reg_num << 18) | value); in arc_mdio_write()

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