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Searched refs:reg_off (Results 1 – 25 of 92) sorted by relevance

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/drivers/clk/meson/
A Ds4-pll.c57 .reg_off = ANACTRL_FIXPLL_CTRL0,
62 .reg_off = ANACTRL_FIXPLL_CTRL0,
67 .reg_off = ANACTRL_FIXPLL_CTRL1,
72 .reg_off = ANACTRL_FIXPLL_CTRL0,
77 .reg_off = ANACTRL_FIXPLL_CTRL0,
82 .reg_off = ANACTRL_FIXPLL_CTRL0,
556 .reg_off = ANACTRL_MPLL_CTRL1,
561 .reg_off = ANACTRL_MPLL_CTRL1,
566 .reg_off = ANACTRL_MPLL_CTRL1,
571 .reg_off = ANACTRL_MPLL_CTRL1,
[all …]
A Da1-pll.c32 .reg_off = ANACTRL_FIXPLL_CTRL0,
37 .reg_off = ANACTRL_FIXPLL_CTRL0,
42 .reg_off = ANACTRL_FIXPLL_CTRL0,
47 .reg_off = ANACTRL_FIXPLL_CTRL1,
52 .reg_off = ANACTRL_FIXPLL_STS,
57 .reg_off = ANACTRL_FIXPLL_CTRL0,
103 .reg_off = ANACTRL_HIFIPLL_CTRL0,
108 .reg_off = ANACTRL_HIFIPLL_CTRL0,
113 .reg_off = ANACTRL_HIFIPLL_CTRL0,
118 .reg_off = ANACTRL_HIFIPLL_CTRL1,
[all …]
A Daxg.c114 .reg_off = HHI_MPLL_CNTL,
119 .reg_off = HHI_MPLL_CNTL,
124 .reg_off = HHI_MPLL_CNTL,
129 .reg_off = HHI_MPLL_CNTL2,
134 .reg_off = HHI_MPLL_CNTL,
139 .reg_off = HHI_MPLL_CNTL,
178 .reg_off = HHI_SYS_PLL_CNTL,
573 .reg_off = HHI_MPLL_CNTL7,
578 .reg_off = HHI_MPLL_CNTL7,
583 .reg_off = HHI_MPLL_CNTL7,
[all …]
A Dc3-pll.c249 .reg_off = ANACTRL_GP0PLL_CTRL0,
254 .reg_off = ANACTRL_GP0PLL_CTRL0,
259 .reg_off = ANACTRL_GP0PLL_CTRL1,
264 .reg_off = ANACTRL_GP0PLL_CTRL0,
269 .reg_off = ANACTRL_GP0PLL_CTRL0,
274 .reg_off = ANACTRL_GP0PLL_CTRL0,
409 .reg_off = ANACTRL_MPLL_CTRL0,
414 .reg_off = ANACTRL_MPLL_CTRL0,
419 .reg_off = ANACTRL_MPLL_CTRL0,
424 .reg_off = ANACTRL_MPLL_CTRL0,
[all …]
A Dg12a-aoclk.c124 .reg_off = AO_RTC_ALT_CLK_CNTL0,
129 .reg_off = AO_RTC_ALT_CLK_CNTL0,
134 .reg_off = AO_RTC_ALT_CLK_CNTL1,
139 .reg_off = AO_RTC_ALT_CLK_CNTL1,
144 .reg_off = AO_RTC_ALT_CLK_CNTL0,
215 .reg_off = AO_CEC_CLK_CNTL_REG0,
220 .reg_off = AO_CEC_CLK_CNTL_REG0,
225 .reg_off = AO_CEC_CLK_CNTL_REG1,
230 .reg_off = AO_CEC_CLK_CNTL_REG1,
235 .reg_off = AO_CEC_CLK_CNTL_REG0,
A Dmeson8-ddr.c28 .reg_off = AM_DDR_PLL_CNTL,
33 .reg_off = AM_DDR_PLL_CNTL,
38 .reg_off = AM_DDR_PLL_CNTL,
43 .reg_off = AM_DDR_PLL_CNTL,
48 .reg_off = AM_DDR_PLL_CNTL,
A Dgxbb.c186 .reg_off = HHI_MPLL_CNTL,
191 .reg_off = HHI_MPLL_CNTL,
196 .reg_off = HHI_MPLL_CNTL,
201 .reg_off = HHI_MPLL_CNTL2,
206 .reg_off = HHI_MPLL_CNTL,
211 .reg_off = HHI_MPLL_CNTL,
815 .reg_off = HHI_MPLL_CNTL7,
820 .reg_off = HHI_MPLL_CNTL,
825 .reg_off = HHI_MPLL_CNTL7,
843 .reg_off = HHI_MPLL_CNTL7,
[all …]
/drivers/mmc/host/
A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
49 #define MIO_EMM_RCA(x) (0xa0 + x->reg_off)
[all …]
/drivers/pinctrl/sunplus/
A Dsppctl.c264 u32 reg_off, bit_off, reg; in sppctl_first_get() local
299 u32 reg_off, bit_off, reg; in sppctl_master_get() local
310 u32 reg_off, bit_off, reg; in sppctl_first_master_set() local
346 u32 reg_off, reg; in sppctl_gpio_input_inv_set() local
355 u32 reg_off, reg; in sppctl_gpio_output_inv_set() local
364 u32 reg_off, bit_off, reg; in sppctl_gpio_output_od_get() local
376 u32 reg_off, reg; in sppctl_gpio_output_od_set() local
417 u32 reg_off, reg; in sppctl_gpio_direction_input() local
433 u32 reg_off, reg; in sppctl_gpio_direction_output() local
467 u32 reg_off, reg; in sppctl_gpio_set() local
[all …]
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_vbif.c61 u32 reg_off; in dpu_hw_set_mem_type() local
81 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
84 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
92 u32 reg_off; in dpu_hw_set_limit_conf() local
96 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_set_limit_conf()
98 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_set_limit_conf()
100 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf()
113 u32 reg_off; in dpu_hw_get_limit_conf() local
118 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_get_limit_conf()
120 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_get_limit_conf()
[all …]
/drivers/pinctrl/
A Dpinctrl-digicolor.c130 int bit_off, reg_off; in dc_set_mux() local
133 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
135 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
138 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
148 int bit_off, reg_off; in dc_pmx_request_gpio() local
151 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
153 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
177 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
179 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
199 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_output()
[all …]
/drivers/gpu/drm/msm/disp/dpu1/catalog/
A Ddpu_1_7_msm8996.h26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
31 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
32 [DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4 },
33 [DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4 },
34 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[all …]
A Ddpu_3_0_msm8998.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
35 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
36 [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
A Ddpu_6_0_sm8250.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
A Ddpu_7_0_sm8350.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
A Ddpu_8_1_sm8450.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
A Ddpu_5_0_sm8150.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
A Ddpu_8_4_sa8775p.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
32 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
A Ddpu_4_0_sdm845.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
A Ddpu_8_0_sc8280xp.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
A Ddpu_5_1_sc8180x.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
A Ddpu_4_1_sdm670.h15 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
16 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
17 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
18 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
19 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
/drivers/net/ethernet/marvell/octeon_ep_vf/
A Doctep_vf_main.h311 #define octep_vf_write_csr(octep_vf_dev, reg_off, value) \ argument
312 writel(value, (octep_vf_dev)->mmio.hw_addr + (reg_off))
314 #define octep_vf_write_csr64(octep_vf_dev, reg_off, val64) \ argument
315 writeq(val64, (octep_vf_dev)->mmio.hw_addr + (reg_off))
317 #define octep_vf_read_csr(octep_vf_dev, reg_off) \ argument
318 readl((octep_vf_dev)->mmio.hw_addr + (reg_off))
320 #define octep_vf_read_csr64(octep_vf_dev, reg_off) \ argument
321 readq((octep_vf_dev)->mmio.hw_addr + (reg_off))
/drivers/pinctrl/realtek/
A Dpinctrl-rtd.c307 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
320 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
332 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
345 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
358 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
366 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
400 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
403 reg_off += 0x4; in rtd_pconf_parse_conf()
421 reg_off += 0x4; in rtd_pconf_parse_conf()
438 reg_off += 0x4; in rtd_pconf_parse_conf()
[all …]
/drivers/net/ethernet/marvell/octeon_ep/
A Doctep_main.h343 #define octep_write_csr(octep_dev, reg_off, value) \ argument
344 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
346 #define octep_write_csr64(octep_dev, reg_off, val64) \ argument
347 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
349 #define octep_read_csr(octep_dev, reg_off) \ argument
350 readl((octep_dev)->mmio[0].hw_addr + (reg_off))
352 #define octep_read_csr64(octep_dev, reg_off) \ argument
353 readq((octep_dev)->mmio[0].hw_addr + (reg_off))

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