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Searched refs:reg_set (Results 1 – 25 of 26) sorted by relevance

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/drivers/media/pci/mgb4/
A Dmgb4_cmt.c196 const u16 *reg_set; in mgb4_cmt_set_vout_freq() local
203 reg_set = cmt_vals_out[index]; in mgb4_cmt_set_vout_freq()
212 mgb4_write_reg(&voutdev->mgbdev->cmt, addr[i], reg_set[i]); in mgb4_cmt_set_vout_freq()
226 const u16 *reg_set; in mgb4_cmt_set_vin_freq_range() local
234 reg_set = cmt_vals_in[freq_range]; in mgb4_cmt_set_vin_freq_range()
243 mgb4_write_reg(&vindev->mgbdev->cmt, addr[i], reg_set[i]); in mgb4_cmt_set_vin_freq_range()
/drivers/scsi/mvsas/
A Dmv_sas.h64 #define SATA_RECEIVED_FIS_LIST(reg_set) \ argument
65 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
66 #define SATA_RECEIVED_SDB_FIS(reg_set) \ argument
67 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
68 #define SATA_RECEIVED_D2H_FIS(reg_set) \ argument
69 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
70 #define SATA_RECEIVED_PIO_FIS(reg_set) \ argument
71 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
72 #define SATA_RECEIVED_DMA_FIS(reg_set) \ argument
73 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
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A Dmv_94xx.c684 if (reg_set > 31) in mvs_94xx_clear_srs_irq()
689 if (tmp & (1 << (reg_set % 32))) { in mvs_94xx_clear_srs_irq()
690 mv_dprintk("register set 0x%x was stopped.\n", reg_set); in mvs_94xx_clear_srs_irq()
691 if (reg_set > 31) in mvs_94xx_clear_srs_irq()
692 mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32)); in mvs_94xx_clear_srs_irq()
694 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_94xx_clear_srs_irq()
744 u8 reg_set = *tfs; in mvs_94xx_free_reg_set() local
749 mvi->sata_reg_set &= ~bit(reg_set); in mvs_94xx_free_reg_set()
750 if (reg_set < 32) in mvs_94xx_free_reg_set()
751 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set); in mvs_94xx_free_reg_set()
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A Dmv_64xx.c124 mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) in mvs_64xx_clear_srs_irq() argument
136 if (tmp & (1 << (reg_set % 32))) { in mvs_64xx_clear_srs_irq()
138 reg_set); in mvs_64xx_clear_srs_irq()
139 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_64xx_clear_srs_irq()
A Dmv_sas.c121 u8 reg_set) in mvs_find_dev_by_reg_set() argument
128 if (mvi->devices[dev_no].taskfileset == reg_set) in mvs_find_dev_by_reg_set()
/drivers/media/i2c/
A Drj54n1cb0c.c895 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1); in rj54n1_set_clock()
1033 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_set_fmt()
1038 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_set_fmt()
1043 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_set_fmt()
1048 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_set_fmt()
1053 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_set_fmt()
1060 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_set_fmt()
1067 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_set_fmt()
1074 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_set_fmt()
1087 ret = reg_set(client, RJ54N1_OCLK_SEL_EN, in rj54n1_set_fmt()
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A Dmt9m111.c140 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) macro
438 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_reset()
440 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); in mt9m111_reset()
828 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); in mt9m111_set_autoexposure()
837 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); in mt9m111_set_autowhitebalance()
917 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_suspend()
919 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | in mt9m111_suspend()
A Dak881x.c46 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
172 reg_set(client, AK881X_VIDEO_PROCESS1, vp1, 0xf); in ak881x_s_std_output()
A Dmt9m001.c125 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
514 ret = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000); in mt9m001_s_ctrl()
/drivers/gpio/
A Dgpio-mmio.c138 return !!(gc->read_reg(gc->reg_set) & pinmask); in bgpio_get_set()
160 *bits |= gc->read_reg(gc->reg_set) & set_mask; in bgpio_get_set_multiple()
244 gc->write_reg(gc->reg_set, mask); in bgpio_set_with_clear()
263 gc->write_reg(gc->reg_set, gc->bgpio_data); in bgpio_set_set()
319 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); in bgpio_set_multiple_set()
333 gc->write_reg(gc->reg_set, set_mask); in bgpio_set_multiple_with_clear()
529 gc->reg_set = set; in bgpio_setup_io()
534 gc->reg_set = set; in bgpio_setup_io()
681 gc->bgpio_data = gc->read_reg(gc->reg_set); in bgpio_init()
/drivers/leds/
A Dleds-tca6507.c154 int reg_set; /* One bit per register where member
269 tca->reg_set |= (1 << bit); in set_select()
290 tca->reg_set |= 1 << reg; in set_code()
351 set = tca->reg_set; in tca6507_work()
353 tca->reg_set = 0; in tca6507_work()
537 if (tca->reg_set) in led_assign()
605 if (tca->reg_set) in tca6507_gpio_set_value()
763 tca->reg_set = 0x7f; in tca6507_probe()
/drivers/scsi/megaraid/
A Dmegaraid_sas_base.c462 regs = instance->reg_set; in megasas_enable_intr_xscale()
479 regs = instance->reg_set; in megasas_disable_intr_xscale()
504 regs = instance->reg_set; in megasas_clear_intr_xscale()
642 regs = instance->reg_set; in megasas_enable_intr_ppc()
661 regs = instance->reg_set; in megasas_disable_intr_ppc()
686 regs = instance->reg_set; in megasas_clear_intr_ppc()
771 regs = instance->reg_set; in megasas_enable_intr_skinny()
790 regs = instance->reg_set; in megasas_disable_intr_skinny()
816 regs = instance->reg_set; in megasas_clear_intr_skinny()
918 regs = instance->reg_set; in megasas_enable_intr_gen2()
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A Dmegaraid_sas_fusion.c107 (instance, instance->reg_set)) in megasas_adp_reset_wait_for_ready()
168 regs = instance->reg_set; in megasas_enable_intr_fusion()
191 regs = instance->reg_set; in megasas_disable_intr_fusion()
205 regs = instance->reg_set; in megasas_clear_intr_fusion()
304 &instance->reg_set->inbound_low_queue_port); in megasas_write_64bit_req_desc()
3997 iounmap(instance->reg_set); in megasas_release_fusion()
4089 &instance->reg_set->fusion_host_diag); in megasas_adp_reset_fusion()
4152 &instance->reg_set->doorbell); in megasas_trigger_snap_dump()
4153 readl(&instance->reg_set->doorbell); in megasas_trigger_snap_dump()
4948 &instance->reg_set->doorbell); in megasas_reset_fusion()
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/drivers/gpu/drm/bridge/
A Dtda998x_drv.c690 reg_set(struct tda998x_priv *priv, u16 reg, u8 val) in reg_set() function
719 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); in tda998x_reset()
847 reg_set(priv, REG_DIP_IF_FLAGS, bit); in tda998x_write_if()
998 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); in tda998x_audio_mute()
1000 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); in tda998x_audio_mute()
1045 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); in tda998x_configure_audio()
1305 reg_set(priv, REG_TX4, TX4_PD_RAM); in tda998x_connector_get_modes()
1551 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); in tda998x_bridge_mode_set()
1594 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); in tda998x_bridge_mode_set()
1674 reg_set(priv, REG_TX33, TX33_HDMI); in tda998x_bridge_mode_set()
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/drivers/pinctrl/mediatek/
A Dpinctrl-mtk-common.c244 unsigned int reg_pupd, reg_set, reg_rst; in mtk_pctrl_spec_pull_set_samereg() local
263 reg_set = spec_pupd_pin->offset + devdata->port_align; in mtk_pctrl_spec_pull_set_samereg()
269 reg_pupd = reg_set; in mtk_pctrl_spec_pull_set_samereg()
283 regmap_write(regmap, reg_set, bit_r0); in mtk_pctrl_spec_pull_set_samereg()
288 regmap_write(regmap, reg_set, bit_r1); in mtk_pctrl_spec_pull_set_samereg()
291 regmap_write(regmap, reg_set, bit_r0); in mtk_pctrl_spec_pull_set_samereg()
292 regmap_write(regmap, reg_set, bit_r1); in mtk_pctrl_spec_pull_set_samereg()
/drivers/media/platform/st/stm32/stm32-dcmipp/
A Ddcmipp-input.c358 reg_set(inp, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE); in dcmipp_inp_configure_parallel()
390 reg_set(inp, DCMIPP_P0FSCR, in dcmipp_inp_configure_csi()
393 reg_set(inp, DCMIPP_P0FSCR, in dcmipp_inp_configure_csi()
A Ddcmipp-common.h167 #define reg_set(device, reg, mask) \ macro
A Ddcmipp-bytecap.c369 reg_set(vcap, DCMIPP_P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); in dcmipp_start_capture()
429 reg_set(vcap, DCMIPP_P0FSCR, DCMIPP_P0FSCR_PIPEN); in dcmipp_bytecap_start_streaming()
443 reg_set(vcap, DCMIPP_CMIER, vcap->cmier); in dcmipp_bytecap_start_streaming()
A Ddcmipp-byteproc.c444 reg_set(byteproc, DCMIPP_P0PPCR, val); in dcmipp_byteproc_configure_scale_crop()
/drivers/media/platform/st/stm32/
A Dstm32-dcmi.c189 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) in reg_set() function
372 reg_set(dcmi->regs, DCMI_CR, CR_CAPTURE); in dcmi_start_capture()
396 reg_set(dcmi->regs, DCMI_CR, CR_CROP); in dcmi_set_crop()
479 reg_set(dcmi->regs, DCMI_ICR, IT_FRAME | IT_OVR | IT_ERR); in dcmi_irq_callback()
778 reg_set(dcmi->regs, DCMI_CR, CR_CM);/* Snapshot mode */ in dcmi_start_streaming()
781 reg_set(dcmi->regs, DCMI_CR, CR_ENABLE); in dcmi_start_streaming()
816 reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); in dcmi_start_streaming()
818 reg_set(dcmi->regs, DCMI_IER, IT_OVR | IT_ERR); in dcmi_start_streaming()
/drivers/i3c/master/mipi-i3c-hci/
A Dhci.h32 #define reg_set(r, v) reg_write(r, reg_read(r) | (v)) macro
A Dcore.c151 reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); in i3c_hci_bus_init()
173 reg_set(HC_CONTROL, HC_CONTROL_RESUME); in mipi_i3c_hci_resume()
770 reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE); in i3c_hci_init()
/drivers/gpu/drm/i915/
A Dintel_uncore.c132 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
133 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
2064 i915_reg_t reg_set, in __fw_domain_init() argument
2079 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set)); in __fw_domain_init()
2084 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset; in __fw_domain_init()
A Dintel_uncore.h186 u32 __iomem *reg_set; member
/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_link.c3659 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR2()
3660 reg_set[i].val); in bnx2x_warpcore_enable_AN_KR2()
3694 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_disable_kr2()
3695 reg_set[i].val); in bnx2x_disable_kr2()
3748 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR()
3749 reg_set[i].val); in bnx2x_warpcore_enable_AN_KR()
3901 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_set_10G_KR()
3902 reg_set[i].val); in bnx2x_warpcore_set_10G_KR()
9668 reg_set[i].reg, reg_set[i].val); in bnx2x_save_848xx_spirom_version()
9757 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_848xx_set_led()
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