Home
last modified time | relevance | path

Searched refs:reg_shift (Results 1 – 25 of 43) sorted by relevance

12

/drivers/input/misc/
A Diqs7222.c811 int reg_shift; member
825 .reg_shift = 8,
833 .reg_shift = 0,
841 .reg_shift = 6,
849 .reg_shift = 5,
856 .reg_shift = 4,
863 .reg_shift = 3,
870 .reg_shift = 0,
886 .reg_shift = 4,
894 .reg_shift = 0,
[all …]
/drivers/gpio/
A Dgpio-adnp.c17 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
18 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
19 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
20 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
21 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
26 unsigned int reg_shift; member
71 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_get()
85 unsigned int reg = offset >> adnp->reg_shift; in __adnp_gpio_set()
114 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_direction_input()
145 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_direction_output()
[all …]
A Dgpio-creg-snps.c34 u32 reg, reg_shift, value; in creg_gpio_set() local
40 reg_shift = layout->shift[offset]; in creg_gpio_set()
42 reg_shift += layout->bit_per_gpio[i] + layout->shift[i]; in creg_gpio_set()
46 reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift); in creg_gpio_set()
47 reg |= (value << reg_shift); in creg_gpio_set()
A Dgpio-htc-egpio.c37 int reg_shift; /* bit shift */ member
123 return bit >> ei->reg_shift; in egpio_pos()
128 return 1 << (bit & ((1 << ei->reg_shift)-1)); in egpio_bit()
189 shift = pos << ei->reg_shift; in egpio_set()
241 shift += (1<<ei->reg_shift)) { in egpio_write_cache()
298 ei->reg_shift = fls(pdata->reg_width - 1); in egpio_probe()
299 pr_debug("reg_shift = %d\n", ei->reg_shift); in egpio_probe()
/drivers/ata/
A Dpata_falcon.c132 int irq = 0, io_offset = 1, reg_shift = 2; /* Falcon defaults */ in pata_falcon_init_one() local
178 reg_shift = 0; in pata_falcon_init_one()
186 ap->ioaddr.error_addr = base + io_offset + (1 << reg_shift); in pata_falcon_init_one()
187 ap->ioaddr.feature_addr = base + io_offset + (1 << reg_shift); in pata_falcon_init_one()
188 ap->ioaddr.nsect_addr = base + io_offset + (2 << reg_shift); in pata_falcon_init_one()
189 ap->ioaddr.lbal_addr = base + io_offset + (3 << reg_shift); in pata_falcon_init_one()
190 ap->ioaddr.lbam_addr = base + io_offset + (4 << reg_shift); in pata_falcon_init_one()
191 ap->ioaddr.lbah_addr = base + io_offset + (5 << reg_shift); in pata_falcon_init_one()
192 ap->ioaddr.device_addr = base + io_offset + (6 << reg_shift); in pata_falcon_init_one()
193 ap->ioaddr.status_addr = base + io_offset + (7 << reg_shift); in pata_falcon_init_one()
[all …]
A Dpata_pxa.c242 (ATA_REG_DATA << pdata->reg_shift); in pxa_ata_probe()
244 (ATA_REG_ERR << pdata->reg_shift); in pxa_ata_probe()
246 (ATA_REG_FEATURE << pdata->reg_shift); in pxa_ata_probe()
248 (ATA_REG_NSECT << pdata->reg_shift); in pxa_ata_probe()
250 (ATA_REG_LBAL << pdata->reg_shift); in pxa_ata_probe()
252 (ATA_REG_LBAM << pdata->reg_shift); in pxa_ata_probe()
254 (ATA_REG_LBAH << pdata->reg_shift); in pxa_ata_probe()
256 (ATA_REG_DEVICE << pdata->reg_shift); in pxa_ata_probe()
258 (ATA_REG_STATUS << pdata->reg_shift); in pxa_ata_probe()
260 (ATA_REG_CMD << pdata->reg_shift); in pxa_ata_probe()
A Dpata_of_platform.c29 unsigned int reg_shift = 0; in pata_of_platform_probe() local
59 of_property_read_u32(dn, "reg-shift", &reg_shift); in pata_of_platform_probe()
76 reg_shift, pio_mask, &pata_platform_sht, in pata_of_platform_probe()
/drivers/net/ethernet/stmicro/stmmac/
A Ddwmac-socfpga.c51 u32 reg_shift; member
108 u32 reg_offset, reg_shift; in socfpga_dwmac_parse_data() local
223 dwmac->reg_shift = reg_shift; in socfpga_dwmac_parse_data()
276 u32 reg_shift = dwmac->reg_shift; in socfpga_gen5_set_phy_mode() local
296 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); in socfpga_gen5_set_phy_mode()
297 ctrl |= val << reg_shift; in socfpga_gen5_set_phy_mode()
305 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); in socfpga_gen5_set_phy_mode()
314 (reg_shift / 2)); in socfpga_gen5_set_phy_mode()
334 u32 reg_shift = dwmac->reg_shift; in socfpga_gen10_set_phy_mode() local
362 module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift); in socfpga_gen10_set_phy_mode()
[all …]
A Dstmmac_mdio.c288 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read_c22()
328 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read_c45()
334 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read_c45()
387 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write_c22()
428 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write_c45()
436 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write_c45()
A Dcommon.h578 unsigned int reg_shift; /* MII reg shift */ member
617 u32 reg_shift; member
/drivers/i2c/busses/
A Di2c-ocores.c35 u32 reg_shift; member
90 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_8()
95 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16()
100 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32()
115 return ioread8(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_8()
120 return ioread16(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_16()
125 return ioread32(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_32()
130 return ioread16be(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_16be()
135 return ioread32be(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_32be()
534 i2c->reg_shift = ilog2(val); in ocores_i2c_of_probe()
[all …]
A Di2c-omap.c183 int reg_shift; /* bit shift for I2C register addresses */ member
271 (omap->regs[reg] << omap->reg_shift)); in omap_i2c_write_reg()
277 (omap->regs[reg] << omap->reg_shift)); in omap_i2c_read_reg()
1388 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; in omap_i2c_probe()
/drivers/pinctrl/
A Dpinctrl-mcp23s08_i2c.c26 mcp->reg_shift = info->reg_shift; in mcp230xx_probe()
50 .reg_shift = 0,
58 .reg_shift = 1,
66 .reg_shift = 1,
A Dpinctrl-mcp23s08_spi.c122 mcp->reg_shift = info->reg_shift; in mcp23s08_spi_regmap_init()
203 .reg_shift = 0,
210 .reg_shift = 1,
218 .reg_shift = 1,
A Dpinctrl-mcp23s08.h30 bool reg_shift; member
36 bool reg_shift; member
A Dpinctrl-mcp23s08.c142 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); in mcp_read()
147 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); in mcp_write()
153 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, in mcp_update_bits()
/drivers/mmc/host/
A Ddw_mmc-pltfm.c27 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ argument
28 ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
74 u32 clk_phase[2] = {0}, reg_offset, reg_shift; in dw_mci_socfpga_priv_init() local
88 of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift); in dw_mci_socfpga_priv_init()
93 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); in dw_mci_socfpga_priv_init()
/drivers/input/touchscreen/
A Diqs7211.c480 int reg_shift; member
506 .reg_shift = 9,
527 .reg_shift = 5,
548 .reg_shift = 0,
566 .reg_shift = 0,
578 .reg_shift = 8,
620 .reg_shift = 8,
630 .reg_shift = 0,
726 .reg_shift = 8,
794 .reg_shift = 7,
[all …]
/drivers/thermal/broadcom/
A Dbrcmstb_thermal.c75 int reg_shift; member
85 .reg_shift = AVS_TMON_INT_THRESH_low_shift,
93 .reg_shift = AVS_TMON_INT_THRESH_high_shift,
101 .reg_shift = AVS_TMON_RESET_THRESH_shift,
198 val >>= trip->reg_shift; in avs_tmon_get_trip_temp()
216 val <<= trip->reg_shift; in avs_tmon_set_trip_temp()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_vbif.c161 u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift; in dpu_hw_set_qos_remap() local
170 reg_shift = (xin_id & 0x7) * 4; in dpu_hw_set_qos_remap()
175 mask = 0x7 << reg_shift; in dpu_hw_set_qos_remap()
178 reg_val |= (remap_level << reg_shift) & mask; in dpu_hw_set_qos_remap()
181 reg_val_lvl |= (remap_level << reg_shift) & mask; in dpu_hw_set_qos_remap()
/drivers/mfd/
A Dtqmx86.c204 void __iomem *io_base, u8 reg_shift) in tqmx86_setup_irq() argument
228 val &= ~(TQMX86_REG_IO_EXT_INT_MASK << reg_shift); in tqmx86_setup_irq()
229 val |= (irq_cfg & TQMX86_REG_IO_EXT_INT_MASK) << reg_shift; in tqmx86_setup_irq()
/drivers/tty/serial/8250/
A D8250_pci.c3624 .reg_shift = 7,
3631 .reg_shift = 7,
3638 .reg_shift = 7,
3647 .reg_shift = 2,
3700 .reg_shift = 2,
3708 .reg_shift = 0,
3720 .reg_shift = 2,
3728 .reg_shift = 2,
3736 .reg_shift = 2,
3744 .reg_shift = 4,
[all …]
/drivers/iio/chemical/
A Dens160_spi.c19 .reg_shift = -1,
/drivers/base/regmap/
A Dinternal.h35 s8 reg_shift; member
124 int reg_shift; member
A Dregmap.c772 map->reg_shift = config->pad_bits % 8; in __regmap_init()
775 map->format.reg_shift = config->reg_shift; in __regmap_init()
866 switch (config->reg_bits + map->reg_shift) { in __regmap_init()
1606 if (map->format.reg_shift > 0) in regmap_reg_addr()
1607 reg >>= map->format.reg_shift; in regmap_reg_addr()
1608 else if (map->format.reg_shift < 0) in regmap_reg_addr()
1609 reg <<= -(map->format.reg_shift); in regmap_reg_addr()
1694 map->format.format_reg(map->work_buf, reg, map->reg_shift); in _regmap_raw_write_impl()
2421 map->format.format_reg(u8, reg, map->reg_shift); in _regmap_raw_multi_reg_write()
2747 map->format.format_reg(map->work_buf, reg, map->reg_shift); in _regmap_raw_read()

Completed in 82 milliseconds

12