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Searched refs:reg_type (Results 1 – 25 of 46) sorted by relevance

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/drivers/comedi/drivers/
A Dni_pcimio.c470 .reg_type = ni_reg_611x,
485 .reg_type = ni_reg_611x,
536 .reg_type = ni_reg_6711,
546 .reg_type = ni_reg_6711,
556 .reg_type = ni_reg_6713,
566 .reg_type = ni_reg_6713,
576 .reg_type = ni_reg_6711,
586 .reg_type = ni_reg_6711,
597 .reg_type = ni_reg_6713,
607 .reg_type = ni_reg_6713,
[all …]
/drivers/gpu/drm/exynos/
A Dexynos_drm_g2d.c562 enum g2d_reg_type reg_type; in g2d_get_reg_type() local
570 reg_type = REG_TYPE_SRC; in g2d_get_reg_type()
580 reg_type = REG_TYPE_DST; in g2d_get_reg_type()
586 reg_type = REG_TYPE_PAT; in g2d_get_reg_type()
589 reg_type = REG_TYPE_MSK; in g2d_get_reg_type()
592 reg_type = REG_TYPE_NONE; in g2d_get_reg_type()
598 return reg_type; in g2d_get_reg_type()
640 if (reg_type != REG_TYPE_SRC && reg_type != REG_TYPE_DST) in g2d_check_buf_desc_is_valid()
694 enum g2d_reg_type reg_type; in g2d_map_cmdlist_gem() local
740 reg_type, in g2d_map_cmdlist_gem()
[all …]
/drivers/memory/
A Dstm32-fmc2-ebi.c230 int reg_type; member
471 switch (reg_type) { in stm32_fmc2_ebi_get_reg()
933 .reg_type = FMC2_REG_BCR,
941 .reg_type = FMC2_REG_BCR,
954 .reg_type = FMC2_REG_BCR,
961 .reg_type = FMC2_REG_BCR,
969 .reg_type = FMC2_REG_BCR,
977 .reg_type = FMC2_REG_BCR,
994 .reg_type = FMC2_REG_BTR,
1002 .reg_type = FMC2_REG_BTR,
[all …]
/drivers/gpio/
A Dgpio-ftgpio010.c91 u32 reg_both, reg_level, reg_type; in ftgpio_gpio_set_irq_type() local
93 reg_type = readl(g->base + GPIO_INT_TYPE); in ftgpio_gpio_set_irq_type()
100 reg_type &= ~mask; in ftgpio_gpio_set_irq_type()
105 reg_type &= ~mask; in ftgpio_gpio_set_irq_type()
111 reg_type &= ~mask; in ftgpio_gpio_set_irq_type()
117 reg_type |= mask; in ftgpio_gpio_set_irq_type()
122 reg_type |= mask; in ftgpio_gpio_set_irq_type()
130 writel(reg_type, g->base + GPIO_INT_TYPE); in ftgpio_gpio_set_irq_type()
A Dgpio-crystalcove.c83 static inline int to_reg(int gpio, enum ctrl_register reg_type) in to_reg() argument
100 if (reg_type == CTRL_IN) { in to_reg()
/drivers/crypto/intel/qat/qat_common/
A Dqat_hal.c1133 switch (reg_type) { in qat_hal_rd_rel_reg()
1205 switch (reg_type) { in qat_hal_wr_rel_reg()
1357 switch (reg_type) { in qat_hal_put_rel_rd_xfer()
1488 type = reg_type - 1; in qat_hal_init_gpr()
1491 type = reg_type; in qat_hal_init_gpr()
1507 enum icp_qat_uof_regtype reg_type, in qat_hal_init_wr_xfer() argument
1522 type = reg_type - 3; in qat_hal_init_wr_xfer()
1525 type = reg_type; in qat_hal_init_wr_xfer()
1542 enum icp_qat_uof_regtype reg_type, in qat_hal_init_rd_xfer() argument
1557 type = reg_type - 3; in qat_hal_init_rd_xfer()
[all …]
A Dadf_common_drv.h163 enum icp_qat_uof_regtype reg_type,
167 enum icp_qat_uof_regtype reg_type,
171 enum icp_qat_uof_regtype reg_type,
A Dicp_qat_uclo.h305 char reg_type; member
337 unsigned char reg_type; member
A Dqat_uclo.c770 enum icp_qat_uof_regtype reg_type, in qat_uclo_init_reg() argument
773 switch (reg_type) { in qat_uclo_init_reg()
780 return qat_hal_init_gpr(handle, ae, ctx_mask, reg_type, in qat_uclo_init_reg()
792 return qat_hal_init_rd_xfer(handle, ae, ctx_mask, reg_type, in qat_uclo_init_reg()
800 return qat_hal_init_wr_xfer(handle, ae, ctx_mask, reg_type, in qat_uclo_init_reg()
805 pr_err("UOF uses not supported reg type 0x%x\n", reg_type); in qat_uclo_init_reg()
834 init_regsym->reg_type, in qat_uclo_init_reg_sym()
848 init_regsym->reg_type, in qat_uclo_init_reg_sym()
/drivers/pinctrl/meson/
A Dpinctrl-amlogic-a4.c278 unsigned int reg_type, in aml_calc_reg_and_bit() argument
283 *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] in aml_calc_reg_and_bit()
284 + bank->pc.bit_offset[reg_type]; in aml_calc_reg_and_bit()
285 *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; in aml_calc_reg_and_bit()
364 unsigned int reg_type) in aml_pinconf_get_gpio_bit() argument
372 aml_calc_reg_and_bit(range, pin, reg_type, &reg, &bit); in aml_pinconf_get_gpio_bit()
517 unsigned int reg_type, in aml_pinconf_set_gpio_bit() argument
525 aml_calc_reg_and_bit(range, pin, reg_type, &reg, &bit); in aml_pinconf_set_gpio_bit()
810 unsigned int reg_type, in aml_gpio_calc_reg_and_bit() argument
815 *bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; in aml_gpio_calc_reg_and_bit()
[all …]
A Dpinctrl-meson.c99 enum meson_reg_type reg_type, in meson_calc_reg_and_bit() argument
102 const struct meson_reg_desc *desc = &bank->regs[reg_type]; in meson_calc_reg_and_bit()
104 *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type]; in meson_calc_reg_and_bit()
182 unsigned int reg_type, in meson_pinconf_set_gpio_bit() argument
193 meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit); in meson_pinconf_set_gpio_bit()
200 unsigned int reg_type) in meson_pinconf_get_gpio_bit() argument
210 meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit); in meson_pinconf_get_gpio_bit()
/drivers/cxl/core/
A Dregs.c274 u8 reg_type = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo); in cxl_decode_regblock() local
282 &pdev->resource[bar], &offset, reg_type); in cxl_decode_regblock()
286 map->reg_type = reg_type; in cxl_decode_regblock()
333 if (map->reg_type == type) { in __cxl_find_regblock_instance()
443 switch (map->reg_type) { in cxl_probe_regs()
/drivers/tty/serial/8250/
A D8250_bcm7271.c248 int reg_type, int offset) in udma_readl() argument
250 return readl(priv->regs[reg_type] + offset); in udma_readl()
254 int reg_type, int offset, u32 value) in udma_writel() argument
256 writel(value, priv->regs[reg_type] + offset); in udma_writel()
260 int reg_type, int offset, u32 bits) in udma_set() argument
262 void __iomem *reg = priv->regs[reg_type] + offset; in udma_set()
271 int reg_type, int offset, u32 bits) in udma_unset() argument
273 void __iomem *reg = priv->regs[reg_type] + offset; in udma_unset()
/drivers/net/ethernet/ibm/ehea/
A Dehea_main.c277 arr[i].reg_type = EHEA_BCMC_BROADCAST | in ehea_update_bcmc_registrations()
283 arr[i].reg_type = EHEA_BCMC_BROADCAST | in ehea_update_bcmc_registrations()
295 arr[i].reg_type = EHEA_BCMC_MULTICAST | in ehea_update_bcmc_registrations()
298 arr[i].reg_type |= EHEA_BCMC_SCOPE_ALL; in ehea_update_bcmc_registrations()
303 arr[i].reg_type = EHEA_BCMC_MULTICAST | in ehea_update_bcmc_registrations()
306 arr[i].reg_type |= EHEA_BCMC_SCOPE_ALL; in ehea_update_bcmc_registrations()
1687 u8 reg_type; in ehea_broadcast_reg_helper() local
1820 u8 reg_type; in ehea_multicast_reg_helper() local
1824 reg_type |= EHEA_BCMC_SCOPE_ALL; in ehea_multicast_reg_helper()
1834 reg_type |= EHEA_BCMC_SCOPE_ALL; in ehea_multicast_reg_helper()
[all …]
A Dehea_phyp.c574 const u8 reg_type, const u64 mc_mac_addr, in ehea_h_reg_dereg_bcmc() argument
581 r6_reg_type = EHEA_BMASK_SET(H_REGBCMC_REGTYPE, reg_type); in ehea_h_reg_dereg_bcmc()
A Dehea.h413 u8 reg_type; /* Registration Type */ member
/drivers/scsi/libsas/
A Dsas_host_smp.c114 u8 reg_type, u8 reg_index, u8 reg_count, in sas_host_smp_write_gpio() argument
125 written = i->dft->lldd_write_gpio(sas_ha, reg_type, reg_index, in sas_host_smp_write_gpio()
/drivers/net/wireless/marvell/mwifiex/
A Ddebugfs.c422 u32 reg_type = 0, reg_offset = 0, reg_value = UINT_MAX; in mwifiex_regrdwr_write() local
428 if (sscanf(buf, "%u %x %x", &reg_type, &reg_offset, &reg_value) != 3) { in mwifiex_regrdwr_write()
433 if (reg_type == 0 || reg_offset == 0) { in mwifiex_regrdwr_write()
437 saved_reg_type = reg_type; in mwifiex_regrdwr_write()
A Dsta_ioctl.c1240 mwifiex_reg_write(struct mwifiex_private *priv, u32 reg_type, in mwifiex_reg_write() argument
1245 reg_rw.type = reg_type; in mwifiex_reg_write()
1259 mwifiex_reg_read(struct mwifiex_private *priv, u32 reg_type, in mwifiex_reg_read() argument
1265 reg_rw.type = reg_type; in mwifiex_reg_read()
/drivers/net/ethernet/broadcom/asp2/
A Dbcmasp.c189 enum asp_netfilt_reg_type reg_type, in bcmasp_netfilt_get_reg_offset() argument
222 switch (reg_type) { in bcmasp_netfilt_get_reg_offset()
236 enum asp_netfilt_reg_type reg_type, in bcmasp_netfilt_wr() argument
245 reg_offset = bcmasp_netfilt_get_reg_offset(priv, nfilt, reg_type, in bcmasp_netfilt_wr()
253 enum asp_netfilt_reg_type reg_type, in bcmasp_netfilt_rd() argument
262 reg_offset = bcmasp_netfilt_get_reg_offset(priv, nfilt, reg_type, in bcmasp_netfilt_rd()
/drivers/scsi/mvsas/
A Dmv_sas.h157 int (*gpio_write)(struct mvs_prv_info *mvs_prv, u8 reg_type,
452 int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
A Dhalbtcoutsrc.h720 void (*btc_set_bt_reg)(void *btc_context, u8 reg_type, u32 offset,
722 u32 (*btc_get_bt_reg)(void *btc_context, u8 reg_type, u32 offset);
/drivers/scsi/isci/
A Dhost.h514 int isci_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
/drivers/net/wireless/intel/iwlwifi/fw/
A Ddbg.c2657 u32 reg_type, dp; in iwl_dump_ini_dump_regions() local
2671 reg_type = reg->type; in iwl_dump_ini_dump_regions()
2672 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) in iwl_dump_ini_dump_regions()
2677 if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY || in iwl_dump_ini_dump_regions()
2678 reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE || in iwl_dump_ini_dump_regions()
2679 reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) && in iwl_dump_ini_dump_regions()
2706 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { in iwl_dump_ini_dump_regions()
2720 &iwl_dump_ini_region_ops[reg_type]); in iwl_dump_ini_dump_regions()
/drivers/net/wireless/intel/iwlwifi/
A Diwl-dbg-tlv.c1330 u32 reg_type; in iwl_dbg_tlv_init_cfg() local
1338 reg_type = reg->type; in iwl_dbg_tlv_init_cfg()
1340 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || in iwl_dbg_tlv_init_cfg()

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