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/drivers/gpu/nova-core/
A Dregs.rs48 register!(NV_PBUS_SW_SCRATCH_0E@0x00001438 {
86 register!(NV_PFB_PRI_MMU_WPR2_ADDR_LO@0x001fa824 {
97 register!(NV_PFB_PRI_MMU_WPR2_ADDR_HI@0x001fa828 {
131 register!(
149 register!(
210 register!(NV_PFALCON_FALCON_RM @ +0x00000084 {
214 register!(NV_PFALCON_FALCON_HWCFG2 @ +0x000000f4 {
227 register!(NV_PFALCON_FALCON_CPUCTL @ +0x00000100 {
237 register!(NV_PFALCON_FALCON_DMACTL @ +0x0000010c {
272 register!(NV_PFALCON_FALCON_HWCFG1 @ +0x0000012c {
[all …]
/drivers/scsi/aic7xxx/
A Daic79xx.reg114 register INTSTAT {
211 register CLRINT {
229 register ERROR {
245 register CLRERR {
261 register HCNTRL {
410 register INTCTL {
515 register HADDR {
547 register HCNT {
802 register OST {
1254 register LQIN {
[all …]
A Daic7xxx.reg68 register SCSISEQ {
196 register SCSIID {
237 register STCNT {
300 register SSTAT0 {
474 register SELID {
657 register ACCUM {
691 register NONE {
698 register FLAGS {
724 register STACK {
736 register BCTL {
[all …]
A DKconfig.aic79xx84 Compile in register value tables for the output of expanded register
/drivers/gpu/nova-core/regs/
A Dmacros.rs88 macro_rules! register { macro
95 register!(@common $name @ $offset $(, $comment)?);
96 register!(@field_accessors $name { $($fields)* });
97 register!(@io $name @ $offset);
107 register!(@field_accessors $name { $($fields)* });
108 register!(@io $name @ $alias::OFFSET);
117 register!(@common $name @ $offset $(, $comment)?);
118 register!(@field_accessors $name { $($fields)* });
119 register!(@io$name @ + $offset);
130 register!(@io $name @ + $alias::OFFSET);
[all …]
/drivers/comedi/drivers/ni_routing/
A DREADME10 register values were exposed and required to be used by users. Several
13 1) The register values are _NOT_ in user documentation, but rather in
14 arcane locations, such as a few register programming manuals that are
18 2) The register values are _NOT_ completely consistent. There is no way to
22 varying purposes, but the end-user had to gain a knowledge of register
32 NIDAQmx(-base) c-libraries, nor with register level programming, _nor_
42 control hardware. In order to facilitate the transfer of register-level
70 V(<value>) : register value is valid, tested, and implemented
71 I(<value>) : register value is implemented but needs testing
72 U(<value>) : register value is not implemented
[all …]
/drivers/mtd/nand/raw/brcmnand/
A DKconfig16 Enables the BRCMNAND glue driver to register the NAND controller
32 Enables the BRCMNAND glue driver to register the NAND controller
39 Enables the BRCMNAND glue driver to register the NAND controller
46 Enables the BRCMNAND controller glue driver to register the NAND
/drivers/mux/
A DKconfig49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
53 MMIO/Regmap register bitfield-controlled Multiplexer controller.
56 a syscon register or a driver regmap register. For N bit wide
/drivers/gpu/drm/msm/
A DNOTES23 up gpu cmdstream to update scanout and write FLUSH register after).
58 register interface is same, just different bases.)
75 freedreno gallium driver. So there may be some mistakes in register
85 parse logged register reads/writes (both from downstream android fbdev
86 driver, and this driver with register logging enabled), as well as to
87 generate the register level headers.
/drivers/staging/media/ipu7/
A DTODO22 Cleanup the register definitions - remove some unnecessary definitions
25 Some ISYS IO sub-blocks register definitions are offset values from
27 to use, need to update the register definitions to make it more clear
/drivers/thermal/intel/
A DKconfig29 Enable this to register CPU digital sensor for package temperature as
42 implements the common set of helper functions to register, get temperature
50 Enable this to register Intel SoCs (e.g. Bay Trail) platform digital
62 Enable this to register Intel Quark SoC (e.g. X1000) platform digital
98 activation temperature via the TCC Offset register, which is widely
/drivers/soc/vt8500/
A DKconfig13 register information. This currently includes just the chip ID register
/drivers/clk/xilinx/
A DKconfig10 register set. This driver also configures the frequency based on the
11 clock information from the logicoreIP register set.
/drivers/i2c/muxes/
A DKconfig95 register based I2C multiplexer. This driver provides access to
97 by a single register.
117 by a CPLD register.
129 configuration register.
/drivers/scsi/
A Dscript_asm.pl156 $register = join ('|', keys %registers);
514 /^($register)\s+(-|$operator)\s+($value)\s*$/i) {
523 } elsif ($src =~ /^($register)\s*$/i) {
552 if ($rest =~ /^($register)\s*(.*)$/i) {
/drivers/net/wireless/marvell/mwifiex/
A DREADME168 This command is used to read/write the adapter register.
176 <offset>: offset of register
180 echo "1 0xa060" > regrdwr : Read the MAC register
181 echo "1 0xa060 0x12" > regrdwr : Write the MAC register
183 : Write 0x80000000 to MAC register
/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
A Dcom.fuc89 // nv_rd32 - read 32-bit value from nv register
91 // In : $r14 register
107 // nv_wr32 - write 32-bit value to nv register
109 // In : $r14 register
/drivers/clk/imgtec/
A DKconfig10 provided register.
/drivers/acpi/numa/
A DKconfig13 register memory initiators with their targets, and export
/drivers/video/fbdev/mmp/hw/
A DKconfig17 will register as a spi master for panel usage
/drivers/phy/ti/
A DKconfig58 the mailbox. The mailbox is present only in omap4 and the register to
60 additional register to power on USB3 PHY/SATA PHY/PCIE PHY
/drivers/nfc/st21nfca/
A DKconfig8 register against it.
/drivers/reset/
A DKconfig79 Registers are located in a shared register region called OLB. EyeQ6H
262 exclusive register space.
297 in a contiguous, exclusive register space. The register is HIWORD_MASKED,
298 which means each register holds 16 reset lines.
/drivers/media/usb/uvc/
A DKconfig19 This option makes USB Video Class devices register an input device
/drivers/gpu/host1x/
A DKconfig15 The Tegra host1x module is the DMA engine for register access to

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