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Searched refs:registers (Results 1 – 25 of 171) sorted by relevance

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/drivers/media/radio/si470x/
A Dradio-si470x-common.c209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
331 radio->registers[POWERCFG] |= POWERCFG_SKMODE; in si470x_set_seek()
333 radio->registers[POWERCFG] |= POWERCFG_SEEKUP; in si470x_set_seek()
354 radio->registers[POWERCFG] &= ~POWERCFG_SEEK; in si470x_set_seek()
372 radio->registers[POWERCFG] = in si470x_start()
390 radio->registers[SYSCONFIG2] = in si470x_start()
401 radio->registers[CHANNEL] & CHANNEL_CHAN); in si470x_start()
423 radio->registers[POWERCFG] &= ~POWERCFG_DMUTE; in si470x_stop()
[all …]
A Dradio-si470x-i2c.c187 radio->registers[SYSCONFIG1] |= 0x1 << 2; in si470x_fops_open()
275 bler = (radio->registers[STATUSRSSI] & in si470x_i2c_interrupt()
277 rds = radio->registers[RDSA]; in si470x_i2c_interrupt()
280 bler = (radio->registers[READCHAN] & in si470x_i2c_interrupt()
282 rds = radio->registers[RDSB]; in si470x_i2c_interrupt()
285 bler = (radio->registers[READCHAN] & in si470x_i2c_interrupt()
287 rds = radio->registers[RDSC]; in si470x_i2c_interrupt()
290 bler = (radio->registers[READCHAN] & in si470x_i2c_interrupt()
292 rds = radio->registers[RDSD]; in si470x_i2c_interrupt()
396 radio->registers[POWERCFG] = POWERCFG_ENABLE; in si470x_i2c_probe()
[all …]
A Dradio-si470x-usb.c388 radio->registers[STATUSRSSI] = in si470x_int_in_callback()
397 radio->registers[STATUSRSSI + regnr] = in si470x_int_in_callback()
412 bler = (radio->registers[STATUSRSSI] & in si470x_int_in_callback()
414 rds = radio->registers[RDSA]; in si470x_int_in_callback()
417 bler = (radio->registers[READCHAN] & in si470x_int_in_callback()
419 rds = radio->registers[RDSB]; in si470x_int_in_callback()
422 bler = (radio->registers[READCHAN] & in si470x_int_in_callback()
424 rds = radio->registers[RDSC]; in si470x_int_in_callback()
427 bler = (radio->registers[READCHAN] & in si470x_int_in_callback()
429 rds = radio->registers[RDSD]; in si470x_int_in_callback()
[all …]
/drivers/scsi/smartpqi/
A Dsmartpqi_sis.c116 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
161 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
185 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
191 registers = ctrl_info->registers; in sis_send_sync_cmd()
194 writel(cmd, &registers->sis_mailbox[0]); in sis_send_sync_cmd()
201 writel(params->mailbox[i], &registers->sis_mailbox[i]); in sis_send_sync_cmd()
205 &registers->sis_ctrl_to_host_doorbell_clear); in sis_send_sync_cmd()
208 writel(~0, &registers->sis_interrupt_mask); in sis_send_sync_cmd()
215 readl(&registers->sis_interrupt_mask); in sis_send_sync_cmd()
236 cmd_status = readl(&registers->sis_mailbox[0]); in sis_send_sync_cmd()
[all …]
/drivers/char/agp/
A Damd-k7-agp.c32 volatile u8 __iomem *registers; member
216 if (!amd_irongate_private.registers) { in amd_irongate_configure()
220 if (!amd_irongate_private.registers) in amd_irongate_configure()
226 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ in amd_irongate_configure()
235 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
237 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
246 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); in amd_irongate_configure()
259 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_cleanup()
261 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_cleanup()
268 iounmap((void __iomem *) amd_irongate_private.registers); in amd_irongate_cleanup()
[all …]
A Dsworks-agp.c39 volatile u8 __iomem *registers; member
240 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); in serverworks_tlbflush()
242 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { in serverworks_tlbflush()
251 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); in serverworks_tlbflush()
253 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { in serverworks_tlbflush()
273 if (!serverworks_private.registers) { in serverworks_configure()
278 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); in serverworks_configure()
284 cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND); in serverworks_configure()
287 writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND); in serverworks_configure()
288 readw(serverworks_private.registers+SVWRKS_COMMAND); in serverworks_configure()
[all …]
A Dintel-gtt.c68 u8 __iomem *registers; member
189 if (!intel_private.registers) in i810_setup()
193 intel_private.registers+I810_PGETBL_CTL); in i810_setup()
197 if ((readl(intel_private.registers+I810_DRAM_CTL) in i810_setup()
580 iounmap(intel_private.registers); in intel_gtt_cleanup()
630 readl(intel_private.registers+I810_PGETBL_CTL) in intel_gtt_init()
652 iounmap(intel_private.registers); in intel_gtt_init()
737 intel_private.registers+I830_HIC); in i830_chipset_flush()
800 reg = intel_private.registers+I810_PGETBL_CTL; in intel_gmch_enable_gtt()
823 if (!intel_private.registers) in i830_setup()
[all …]
A Dati-agp.c51 volatile u8 __iomem *registers; member
178 writel(1, ati_generic_private.registers+ATI_GART_CACHE_CNTRL); in ati_tlbflush()
179 readl(ati_generic_private.registers+ATI_GART_CACHE_CNTRL); /* PCI Posting. */ in ati_tlbflush()
199 iounmap((volatile u8 __iomem *)ati_generic_private.registers); in ati_cleanup()
210 ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); in ati_configure()
212 if (!ati_generic_private.registers) in ati_configure()
226 writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID); in ati_configure()
227 readl(ati_generic_private.registers+ATI_GART_FEATURE_ID); /* PCI Posting.*/ in ati_configure()
234 writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers+ATI_GART_BASE); in ati_configure()
235 readl(ati_generic_private.registers+ATI_GART_BASE); /* PCI Posting. */ in ati_configure()
/drivers/gpio/
A Dgpio-74x164.c25 u32 registers; member
33 u8 buffer[] __counted_by(registers);
39 chip->registers); in __gen_74x164_write_config()
45 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_get_value()
57 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_value()
81 for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) { in gen_74x164_set_multiple()
82 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_multiple()
135 chip->registers = nregs; in gen_74x164_probe()
147 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; in gen_74x164_probe()
/drivers/gpu/drm/msm/adreno/
A Da6xx_gpu_state.c33 struct a6xx_gpu_state_obj *registers; member
1133 regs->registers[i] + j); in a6xx_get_ahb_gpu_registers()
1304 if (!a6xx_state->registers) in a6xx_get_registers()
1311 &a6xx_state->registers[index++]); in a6xx_get_registers()
1339 &a6xx_state->registers[index++], in a6xx_get_registers()
1390 if (!a6xx_state->registers) in a7xx_get_registers()
1689 u32 count = RANGE(registers, i); in a6xx_show_registers()
1690 u32 offset = registers[i]; in a6xx_show_registers()
1709 u32 count = RANGE(registers, i); in a7xx_show_registers_indented()
1710 u32 offset = registers[i]; in a7xx_show_registers_indented()
[all …]
A Dadreno_gpu.c797 if (!adreno_gpu->registers) in adreno_gpu_state_get()
802 count += adreno_gpu->registers[i + 1] - in adreno_gpu_state_get()
803 adreno_gpu->registers[i] + 1; in adreno_gpu_state_get()
806 if (state->registers) { in adreno_gpu_state_get()
810 u32 start = adreno_gpu->registers[i]; in adreno_gpu_state_get()
811 u32 end = adreno_gpu->registers[i + 1]; in adreno_gpu_state_get()
815 state->registers[pos++] = addr; in adreno_gpu_state_get()
840 kfree(state->registers); in adreno_gpu_state_destroy()
1024 state->registers[i * 2] << 2, in adreno_show()
1025 state->registers[(i * 2) + 1]); in adreno_show()
[all …]
/drivers/hv/
A Dmshv_common.c28 struct hv_register_assoc *registers) in hv_call_get_vp_registers() argument
52 input_page->names[i] = registers[i].name; in hv_call_get_vp_registers()
61 registers[i].value = output_page[i]; in hv_call_get_vp_registers()
63 registers += completed; in hv_call_get_vp_registers()
74 struct hv_register_assoc *registers) in hv_call_set_vp_registers() argument
94 memcpy(input_page->elements, registers, in hv_call_set_vp_registers()
103 registers += completed; in hv_call_set_vp_registers()
/drivers/gpu/drm/msm/
A DMakefile175 $(headergen-opts) --rnn $(src)/registers --xml $< c-defines > $@
177 $(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
178 $(src)/registers/adreno/adreno_common.xml \
179 $(src)/registers/adreno/adreno_pm4.xml \
180 $(src)/registers/freedreno_copyright.xml \
181 $(src)/registers/gen_header.py \
182 $(src)/registers/rules-fd.xsd \
186 $(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
187 $(src)/registers/freedreno_copyright.xml \
188 $(src)/registers/gen_header.py \
[all …]
/drivers/media/platform/rockchip/rkisp1/
A Drkisp1-debug.c67 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_core_regs_show() local
83 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_core_regs_show()
89 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_isp_regs_show() local
103 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_isp_regs_show()
109 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_rsz_regs_show() local
124 return rkisp1_debug_dump_regs(rsz->rkisp1, m, rsz->regs_base, registers); in rkisp1_debug_dump_rsz_regs_show()
130 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_mi_mp_show() local
142 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_mi_mp_show()
/drivers/usb/storage/
A Dshuttle_usbat.c592 data[j<<1] = registers[j]; in usbat_hp8200e_rw_block_test()
678 unsigned char *registers, in usbat_multiple_write() argument
709 data[i<<1] = registers[i]; in usbat_multiple_write()
1054 unsigned char registers[3] = { in usbat_flash_get_sector_count() local
1112 unsigned char registers[7] = { in usbat_flash_read_data() local
1305 registers, data, 19, in usbat_hp8200e_handle_read10()
1374 registers, data, 19, in usbat_hp8200e_handle_read10()
1556 unsigned char registers[32]; in usbat_hp8200e_transport() local
1575 registers[6] = USBAT_ATA_CMD; in usbat_hp8200e_transport()
1585 registers[i] = 0x10; in usbat_hp8200e_transport()
[all …]
/drivers/char/xillybus/
A Dxillybus_core.c147 ep->registers + fpga_msg_ctrl_reg); in xillybus_isr()
803 channel->endpoint->registers + in xillybus_read()
888 channel->endpoint->registers + in xillybus_read()
894 channel->endpoint->registers + in xillybus_read()
983 channel->endpoint->registers + in xillybus_read()
1338 channel->endpoint->registers + in xillybus_write()
1344 channel->endpoint->registers + in xillybus_write()
1522 channel->endpoint->registers + in xillybus_open()
1543 channel->endpoint->registers + in xillybus_open()
1587 channel->endpoint->registers + in xillybus_release()
[all …]
A Dxillybus_of.c50 endpoint->registers = devm_platform_ioremap_resource(op, 0); in xilly_drv_probe()
51 if (IS_ERR(endpoint->registers)) in xilly_drv_probe()
52 return PTR_ERR(endpoint->registers); in xilly_drv_probe()
/drivers/net/dsa/mv88e6xxx/
A Ddevlink.c272 u16 *registers; in mv88e6xxx_region_global_snapshot() local
275 registers = kmalloc_array(32, sizeof(u16), GFP_KERNEL); in mv88e6xxx_region_global_snapshot()
276 if (!registers) in mv88e6xxx_region_global_snapshot()
283 err = mv88e6xxx_g1_read(chip, i, &registers[i]); in mv88e6xxx_region_global_snapshot()
286 err = mv88e6xxx_g2_read(chip, i, &registers[i]); in mv88e6xxx_region_global_snapshot()
293 kfree(registers); in mv88e6xxx_region_global_snapshot()
297 *data = (u8 *)registers; in mv88e6xxx_region_global_snapshot()
619 u16 *registers; in mv88e6xxx_region_port_snapshot() local
623 if (!registers) in mv88e6xxx_region_port_snapshot()
630 kfree(registers); in mv88e6xxx_region_port_snapshot()
[all …]
/drivers/media/platform/nxp/imx8-isi/
A Dimx8-isi-debug.c29 static const struct debug_regs registers[] = { in mxc_isi_debug_dump_regs_show() local
90 for (i = 0; i < ARRAY_SIZE(registers); ++i) in mxc_isi_debug_dump_regs_show()
92 registers[i].name, registers[i].offset, in mxc_isi_debug_dump_regs_show()
93 mxc_isi_read(pipe, registers[i].offset)); in mxc_isi_debug_dump_regs_show()
/drivers/thermal/ti-soc-thermal/
A Ddra752-thermal-data.c334 .registers = &dra752_mpu_temp_sensor_registers,
343 .registers = &dra752_gpu_temp_sensor_registers,
350 .registers = &dra752_core_temp_sensor_registers,
357 .registers = &dra752_dspeve_temp_sensor_registers,
364 .registers = &dra752_iva_temp_sensor_registers,
A Domap4-thermal-data.c72 .registers = &omap4430_mpu_temp_sensor_registers,
203 .registers = &omap4460_mpu_temp_sensor_registers,
234 .registers = &omap4460_mpu_temp_sensor_registers,
/drivers/iio/adc/
A Dat91_adc.c137 (st->registers->channel_base + (ch * 4))
212 struct at91_adc_reg_desc registers; member
227 const struct at91_adc_reg_desc *registers; member
391 at91_adc_writel(st, st->registers->trigger_register, in at91_adc_rl_interrupt()
566 const struct at91_adc_reg_desc *reg = st->registers; in at91_adc_configure_trigger()
1040 st->registers = &st->caps->registers; in at91_adc_probe()
1234 .registers = {
1259 .registers = {
1277 .registers = {
1298 .registers = {
[all …]
/drivers/scsi/aic7xxx/aicasm/
A Daicasm_symbol.c468 symlist_t registers; in symtable_dump() local
485 SLIST_INIT(&registers); in symtable_dump()
500 symlist_add(&registers, cursym, SYMLIST_SORT); in symtable_dump()
537 SLIST_FOREACH(curnode, &registers, links) { in symtable_dump()
585 regnode = symlist_search(&registers, regname); in symtable_dump()
597 regnode = symlist_search(&registers, regname); in symtable_dump()
602 while (SLIST_FIRST(&registers) != NULL) { in symtable_dump()
608 curnode = SLIST_FIRST(&registers); in symtable_dump()
609 SLIST_REMOVE_HEAD(&registers, links); in symtable_dump()
/drivers/firewire/
A Dinit_ohci1394_dma.c37 void __iomem *registers; member
42 writel(data, ohci->registers + offset); in reg_write()
47 return readl(ohci->registers + offset); in reg_read()
248 ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE); in init_ohci1394_controller()
/drivers/platform/x86/intel/pmc/
A DKconfig14 to Power Management Controller registers via various interfaces. This
25 - SLPS0 Debug registers (Cannonlake/Icelake PCH)
26 - Low Power Mode registers (Tigerlake and beyond)

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