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Searched refs:regp (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv04/
A Dhw.c462 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, in nv_save_state_ramdac()
480 clk->pll_prog(clk, pllreg, &regp->pllvals); in nv_load_state_ramdac()
549 rd_cio_state(dev, head, regp, i); in nv_save_state_vga()
577 wr_cio_state(dev, head, regp, i); in nv_load_state_vga()
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); in nv_save_state_ext()
610 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_save_state_ext()
613 rd_cio_state(dev, head, regp, 0x9f); in nv_save_state_ext()
615 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_save_state_ext()
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_save_state_ext()
726 wr_cio_state(dev, head, regp, 0x9f); in nv_load_state_ext()
[all …]
A Dcrtc.c87 regp->ramdac_634 = level; in nv_crtc_set_image_sharpening()
308 regp->MiscOutReg = 0x23; in nv_crtc_mode_set_vga()
310 regp->MiscOutReg |= 0x40; in nv_crtc_mode_set_vga()
312 regp->MiscOutReg |= 0x80; in nv_crtc_mode_set_vga()
390 regp->CRTC[NV_CIO_CRE_42] = in nv_crtc_mode_set_vga()
429 regp->Attribute[1] = 0x01; in nv_crtc_mode_set_vga()
496 regp->crtc_eng_ctrl = 0; in nv_crtc_mode_set_regs()
598 regp->tv_setup = 0; in nv_crtc_mode_set_regs()
603 regp->ramdac_8c0 = 0x100; in nv_crtc_mode_set_regs()
604 regp->ramdac_a20 = 0x0; in nv_crtc_mode_set_regs()
[all …]
A Ddfp.c319 regp->fp_vert_regs[FP_VALID_START] = 0; in nv04_dfp_mode_set()
344 regp->fp_control |= (2 << 24); in nv04_dfp_mode_set()
356 regp->fp_control |= (8 << 28); in nv04_dfp_mode_set()
359 regp->fp_control |= (8 << 28); in nv04_dfp_mode_set()
370 regp->fp_debug_1 = 0; in nv04_dfp_mode_set()
372 regp->fp_debug_2 = 0; in nv04_dfp_mode_set()
422 regp->dither = savep->dither | 0x00010000; in nv04_dfp_mode_set()
427 regp->dither_regs[i] = 0xe4e4e4e4; in nv04_dfp_mode_set()
428 regp->dither_regs[i + 3] = 0x44444444; in nv04_dfp_mode_set()
440 regp->dither = savep->dither; in nv04_dfp_mode_set()
[all …]
A Dcursor.c42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_cursor_set_offset() local
45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = in nv04_cursor_set_offset()
48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = in nv04_cursor_set_offset()
51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= in nv04_cursor_set_offset()
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; in nv04_cursor_set_offset()
55 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv04_cursor_set_offset()
56 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv04_cursor_set_offset()
57 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv04_cursor_set_offset()
A Dtvnv04.c146 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_tv_mode_set() local
148 regp->tv_htotal = adjusted_mode->htotal; in nv04_tv_mode_set()
149 regp->tv_vtotal = adjusted_mode->vtotal; in nv04_tv_mode_set()
155 regp->tv_hskew = 1; in nv04_tv_mode_set()
156 regp->tv_hsync_delay = 1; in nv04_tv_mode_set()
157 regp->tv_hsync_delay2 = 64; in nv04_tv_mode_set()
158 regp->tv_vskew = 1; in nv04_tv_mode_set()
159 regp->tv_vsync_delay = 1; in nv04_tv_mode_set()
/drivers/video/fbdev/
A Dcg3.c330 u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]]; in cg3_do_default_mode() local
331 sbus_writeb(p[1], regp); in cg3_do_default_mode()
334 u8 __iomem *regp; in cg3_do_default_mode() local
336 regp = (u8 __iomem *)&par->regs->cmap.addr; in cg3_do_default_mode()
337 sbus_writeb(p[0], regp); in cg3_do_default_mode()
338 regp = (u8 __iomem *)&par->regs->cmap.control; in cg3_do_default_mode()
339 sbus_writeb(p[1], regp); in cg3_do_default_mode()
A Dbw2.c264 u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]]; in bw2_do_default_mode() local
265 sbus_writeb(p[1], regp); in bw2_do_default_mode()
/drivers/i3c/master/
A Dast2600-i3c-master.c53 static int ast2600_i3c_pullup_to_reg(unsigned int ohms, u32 *regp) in ast2600_i3c_pullup_to_reg() argument
71 if (regp) in ast2600_i3c_pullup_to_reg()
72 *regp = reg; in ast2600_i3c_pullup_to_reg()
/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
A Dchan.h39 unsigned regp; member
A Dnv04.c67 u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; in nv04_chan_stop()
75 nvkm_wr32(device, c->regp, 0x00000000); in nv04_chan_stop()
/drivers/edac/
A Dpnd2_edac.c291 #define RD_REGP(regp, regname, port) \ argument
295 regp, sizeof(struct regname), \
298 #define RD_REG(regp, regname) \ argument
302 regp, sizeof(struct regname), \
/drivers/net/ethernet/amd/
A Datarilance.c404 static noinline int __init addr_accessible(volatile void *regp, int wordflag, in addr_accessible() argument
443 : "a" (regp), "a" (&vbr[2]), "rm" (wordflag), "rm" (writeflag) in addr_accessible()
/drivers/hwmon/
A Dnct6775-core.c3473 static int add_temp_sensors(struct nct6775_data *data, const u16 *regp, in add_temp_sensors() argument
3482 if (!regp[i]) in add_temp_sensors()
3484 err = nct6775_read_value(data, regp[i], &src); in add_temp_sensors()

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