| /drivers/scsi/aic7xxx/ |
| A D | aic79xx_reg_print.c_shipped | 27 0x01, regvalue, cur_col, wrap));
39 0x0b, regvalue, cur_col, wrap));
54 0x0c, regvalue, cur_col, wrap));
72 0x18, regvalue, cur_col, wrap));
93 0x19, regvalue, cur_col, wrap));
110 0x1a, regvalue, cur_col, wrap));
124 0x1b, regvalue, cur_col, wrap));
139 0x3a, regvalue, cur_col, wrap));
155 0x3b, regvalue, cur_col, wrap));
171 0x3f, regvalue, cur_col, wrap));
[all …]
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| A D | aic7xxx_reg_print.c_shipped | 26 0x00, regvalue, cur_col, wrap));
43 0x01, regvalue, cur_col, wrap));
70 0x03, regvalue, cur_col, wrap));
86 0x04, regvalue, cur_col, wrap));
105 0x0b, regvalue, cur_col, wrap));
123 0x0c, regvalue, cur_col, wrap));
141 0x0d, regvalue, cur_col, wrap));
154 0x0e, regvalue, cur_col, wrap));
172 0x10, regvalue, cur_col, wrap));
190 0x11, regvalue, cur_col, wrap));
[all …]
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| A D | aic79xx_reg.h_shipped | 18 #define ahd_intstat_print(regvalue, cur_col, wrap) \
25 #define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \
32 #define ahd_seqintstat_print(regvalue, cur_col, wrap) \
39 #define ahd_intctl_print(regvalue, cur_col, wrap) \
46 #define ahd_dfcntrl_print(regvalue, cur_col, wrap) \
53 #define ahd_dfstatus_print(regvalue, cur_col, wrap) \
81 #define ahd_dffstat_print(regvalue, cur_col, wrap) \
109 #define ahd_selid_print(regvalue, cur_col, wrap) \
123 #define ahd_sstat0_print(regvalue, cur_col, wrap) \
130 #define ahd_sstat1_print(regvalue, cur_col, wrap) \
[all …]
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| A D | aic7xxx_reg.h_shipped | 18 #define ahc_scsiseq_print(regvalue, cur_col, wrap) \
25 #define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \
32 #define ahc_scsisigi_print(regvalue, cur_col, wrap) \
39 #define ahc_scsirate_print(regvalue, cur_col, wrap) \
46 #define ahc_sstat0_print(regvalue, cur_col, wrap) \
53 #define ahc_sstat1_print(regvalue, cur_col, wrap) \
60 #define ahc_sstat2_print(regvalue, cur_col, wrap) \
67 #define ahc_sstat3_print(regvalue, cur_col, wrap) \
74 #define ahc_simode0_print(regvalue, cur_col, wrap) \
116 #define ahc_seqctl_print(regvalue, cur_col, wrap) \
[all …]
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| /drivers/hwmon/ |
| A D | gl518sm.c | 306 int regvalue; \
313 regvalue = gl518_read_value(client, reg); \
315 regvalue = (regvalue & ~mask) | (data->value << shift); \
316 gl518_write_value(client, reg, regvalue); \
347 int regvalue; in fan_min_store() local
356 regvalue = gl518_read_value(client, GL518_REG_FAN_LIMIT); in fan_min_store()
358 regvalue = (regvalue & (0xff << (8 * nr))) in fan_min_store()
381 int regvalue; in fan_div_store() local
410 regvalue = gl518_read_value(client, GL518_REG_MISC); in fan_div_store()
412 regvalue = (regvalue & ~(0xc0 >> (2 * nr))) in fan_div_store()
[all …]
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| /drivers/clk/mstar/ |
| A D | clk-msc313-cpupll.c | 89 static void msc313_cpupll_setfreq(struct msc313_cpupll *cpupll, u32 regvalue) in msc313_cpupll_setfreq() argument
93 msc313_cpupll_reg_write32(cpupll, REG_LPF_HIGH_BOTTOM, regvalue); in msc313_cpupll_setfreq()
114 msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, regvalue); in msc313_cpupll_setfreq()
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| /drivers/net/ethernet/intel/igb/ |
| A D | e1000_mac.c | 1620 u32 i, regvalue = 0; in igb_write_8bit_ctrl_reg() local
1624 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); in igb_write_8bit_ctrl_reg()
1625 wr32(reg, regvalue); in igb_write_8bit_ctrl_reg()
1630 regvalue = rd32(reg); in igb_write_8bit_ctrl_reg()
1631 if (regvalue & E1000_GEN_CTL_READY) in igb_write_8bit_ctrl_reg()
1634 if (!(regvalue & E1000_GEN_CTL_READY)) { in igb_write_8bit_ctrl_reg()
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| /drivers/mmc/host/ |
| A D | vub300.c | 291 unsigned regvalue:8; member
554 vub300->sdio_register[i].regvalue = in add_offloaded_reg()
1875 u8 rsp3 = vub300->sdio_register[i].regvalue; in satisfy_request_from_offloaded_data()
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