| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 710 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
745 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1006 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1036 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1049 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1061 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1085 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1209 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1387 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_construct()
1432 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 672 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
707 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
951 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
981 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
994 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1006 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1030 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1151 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1320 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_construct()
1365 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 1055 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1085 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1098 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1103 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1110 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1133 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1178 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1203 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1424 pool->base.res_cap = &res_cap_dcn301; in dcn301_resource_construct()
1655 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 1381 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1411 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1424 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1436 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1459 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1509 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1534 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
1739 pool->base.res_cap = &res_cap_dcn31; in dcn316_resource_construct()
1909 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_construct()
1959 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 1443 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1472 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1485 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1497 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1520 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1573 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1598 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
1823 pool->base.res_cap = &res_cap_dcn314; in dcn314_resource_construct()
2008 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_construct()
2066 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 1385 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1415 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1428 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1463 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1516 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
1893 pool->base.res_cap = &res_cap_dcn31; in dcn31_resource_construct()
2085 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_construct()
2143 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 1454 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_destruct()
1484 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn35_resource_destruct()
1497 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn35_resource_destruct()
1509 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1532 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn35_resource_destruct()
1601 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1640 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
1828 pool->base.res_cap = &res_cap_dcn35; in dcn35_resource_construct()
2043 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn35_resource_construct()
2101 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 1385 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1415 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1428 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1463 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1516 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
1863 pool->base.res_cap = &res_cap_dcn31; in dcn315_resource_construct()
2033 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_construct()
2091 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 1434 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_destruct()
1464 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn351_resource_destruct()
1477 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn351_resource_destruct()
1489 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1512 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn351_resource_destruct()
1581 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1620 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
1800 pool->base.res_cap = &res_cap_dcn351; in dcn351_resource_construct()
2014 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn351_resource_construct()
2072 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 1435 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn36_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn36_resource_destruct()
1478 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn36_resource_destruct()
1490 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn36_resource_destruct()
1513 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn36_resource_destruct()
1582 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1621 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
1801 pool->base.res_cap = &res_cap_dcn36; in dcn36_resource_construct()
2016 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn36_resource_construct()
2074 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn36_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 1084 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1114 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1127 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1139 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1218 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1243 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1443 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
2291 pool->base.res_cap = &res_cap_dcn3; in dcn30_resource_construct()
2486 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_construct()
2535 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| A D | dce60_resource.c | 372 static const struct resource_caps res_cap = { variable
822 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
952 pool->base.res_cap = &res_cap; in dce60_construct()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
961 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1076 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1150 pool->base.res_cap = &res_cap_61; in dce61_construct()
1274 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1348 pool->base.res_cap = &res_cap_64; in dce64_construct()
1471 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| A D | dce80_resource.c | 374 static const struct resource_caps res_cap = { variable
828 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
958 pool->base.res_cap = &res_cap; in dce80_construct()
966 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
967 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1160 pool->base.res_cap = &res_cap_81; in dce81_construct()
1286 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1360 pool->base.res_cap = &res_cap_83; in dce83_construct()
1483 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 1372 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1401 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1414 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1426 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1487 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1516 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1672 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
1674 num_pipes = pool->base.res_cap->num_timing_generator; in dcn321_resource_construct()
1939 …pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_… in dcn321_resource_construct()
1947 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 1393 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn401_resource_destruct()
1423 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn401_resource_destruct()
1436 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn401_resource_destruct()
1448 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn401_resource_destruct()
1509 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_dwbc_create()
1540 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_mmhubbub_create()
1849 pool->base.res_cap = &res_cap_dcn4_01; in dcn401_resource_construct()
1852 num_pipes = pool->base.res_cap->num_timing_generator; in dcn401_resource_construct()
2130 …pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_… in dcn401_resource_construct()
2138 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn401_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_link_enc_cfg.c | 40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
168 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
262 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
539 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
695 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) { in link_enc_cfg_validate()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 1390 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1420 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1433 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1506 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1535 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1626 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
2164 pool->base.res_cap = &res_cap_dcn32; in dcn32_resource_construct()
2440 …pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_ca… in dcn32_resource_construct()
2448 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| A D | dce100_resource.c | 374 static const struct resource_caps res_cap = { variable
781 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
993 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1068 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1069 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1125 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 1093 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1123 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1136 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1148 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1338 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1352 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1366 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2240 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2263 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
2411 pool->base.res_cap = &res_cap_nv14; in dcn20_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| A D | dce120_resource.c | 498 static const struct resource_caps res_cap = { variable
626 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1075 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1079 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1080 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1225 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 664 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
693 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
706 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
711 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
718 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1397 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1407 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1620 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
1656 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 949 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
954 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1096 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1194 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1229 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1238 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1254 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 489 static const struct resource_caps res_cap = { variable
944 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1328 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1330 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1344 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1610 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| A D | dce112_resource.c | 802 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1233 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1240 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1241 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1375 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| A D | dcn201_hwseq.c | 186 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
297 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
330 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
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