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Searched refs:res_ctx (Results 1 – 25 of 94) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/core/
A Ddc_link_enc_cfg.c110 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] = eng_id; in remove_link_enc_assignment()
169 eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i]; in find_first_avail_link_enc()
178 eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i]; in find_first_avail_link_enc()
276 state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; in link_enc_cfg_init()
281 memcpy(&dst_ctx->res_ctx.link_enc_cfg_ctx, in link_enc_cfg_copy()
282 &src_ctx->res_ctx.link_enc_cfg_ctx, in link_enc_cfg_copy()
283 sizeof(dst_ctx->res_ctx.link_enc_cfg_ctx)); in link_enc_cfg_copy()
401 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in link_enc_cfg_link_encs_assign()
420 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in link_enc_cfg_link_encs_assign()
433 state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; in link_enc_cfg_link_encs_assign()
[all …]
A Ddc_resource.c2364 &state->res_ctx, in resource_log_pipe_for_stream()
2730 const struct resource_context *res_ctx = &dc->current_state->res_ctx; in is_dio_enc_acquired_by_other_link() local
2747 struct resource_context *res_ctx = &context->res_ctx; in swap_dio_link_enc_to_muxable_ctx() local
2770 struct resource_context *res_ctx = &context->res_ctx; in add_dio_link_enc_to_ctx() local
2857 &context->res_ctx, in resource_remove_otg_master_for_stream_output()
2876 &context->res_ctx, in resource_remove_otg_master_for_stream_output()
3808 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool); in acquire_otg_master_pipe_for_stream()
3815 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool); in acquire_otg_master_pipe_for_stream()
3823 &cur_ctx->res_ctx, &new_ctx->res_ctx, pool); in acquire_otg_master_pipe_for_stream()
5231 const struct resource_context *res_ctx = &dc->current_state->res_ctx; in get_temp_dp_link_res() local
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A Ddc_stream.c232 struct resource_context *res_ctx; in program_cursor_attributes() local
238 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
361 struct resource_context *res_ctx; in program_cursor_position() local
367 res_ctx = &dc->current_state->res_ctx; in program_cursor_position()
640 struct resource_context *res_ctx = in dc_stream_get_vblank_counter() local
641 &dc->current_state->res_ctx; in dc_stream_get_vblank_counter()
663 struct resource_context *res_ctx; in dc_stream_send_dp_sdp() local
671 res_ctx = &dc->current_state->res_ctx; in dc_stream_send_dp_sdp()
703 struct resource_context *res_ctx = in dc_stream_get_scanoutpos() local
704 &dc->current_state->res_ctx; in dc_stream_get_scanoutpos()
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A Ddc.c691 &dc->current_state->res_ctx, stream); in dc_stream_configure_crc()
1411 pipe = &context->res_ctx.pipe_ctx[i]; in disable_vbios_mode_if_required()
1578 …if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event… in enable_timing_multisync()
1601 if (!ctx->res_ctx.pipe_ctx[i].stream in program_timing_sync()
2062 pipe = &context->res_ctx.pipe_ctx[i]; in determine_pipe_unlock_order()
2166 pipe = &context->res_ctx.pipe_ctx[i]; in dc_commit_state_no_check()
2442 struct resource_context *res_ctx = &dc->current_state->res_ctx; in dc_acquire_release_mpc_3dlut() local
2445 if (pool && res_ctx) { in dc_acquire_release_mpc_3dlut()
3949 &context->res_ctx, in commit_planes_for_stream_fast()
4084 &context->res_ctx, in commit_planes_for_stream()
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A Ddc_surface.c74 struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; in dc_plane_get_pipe_mask()
135 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
150 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
290 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_force_dcc_and_tiling_disable()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_dc_resource_mgmt.c114 …if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id… in find_master_pipe_of_stream()
115 if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe) in find_master_pipe_of_stream()
116 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_stream()
130 …if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].… in find_master_pipe_of_plane()
131 state->res_ctx.pipe_ctx[i].stream->stream_id, in find_master_pipe_of_plane()
134 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_plane()
267 …if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stre… in find_preferred_pipe_candidates()
381 pipe = &state->res_ctx.pipe_ctx[i]; in find_more_pipes_for_stream()
447 pipe = &state->res_ctx.pipe_ctx[i]; in find_more_free_pipes()
714 free_pipe(&state->res_ctx.pipe_ctx[i]); in free_unused_pipes_for_plane()
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A Ddml2_utils.c174 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
176 if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
299 if (!context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream) in dml2_calculate_rq_and_dlg_params()
306 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id, in dml2_calculate_rq_and_dlg_params()
327 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false; in dml2_calculate_rq_and_dlg_params()
347 …if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_i… in dml2_calculate_rq_and_dlg_params()
348 (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe == NULL || in dml2_calculate_rq_and_dlg_params()
349 …context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_… in dml2_calculate_rq_and_dlg_params()
440 if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) { in dml2_extract_writeback_wm()
520 if (!display_state->res_ctx.pipe_ctx[i].stream) in dml2_verify_det_buffer_configuration()
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A Ddml2_mall_phantom.c50 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dml2_helper_calculate_num_ways_for_subvp()
107 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in merge_pipes_for_subvp()
192 struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; in get_num_free_pipes()
238 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in assign_subvp_pipe()
263 pipe = &context->res_ctx.pipe_ctx[i]; in assign_subvp_pipe()
316 struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; in enough_pipes_for_subvp()
449 pipe = &context->res_ctx.pipe_ctx[i]; in dml2_svp_drr_schedulable()
534 pipe = &context->res_ctx.pipe_ctx[i]; in subvp_vblank_schedulable()
665 pipe = &state->res_ctx.pipe_ctx[i]; in set_phantom_stream_timing()
796 struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; in add_phantom_pipes_for_main_pipe()
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A Ddml2_wrapper.h75 void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master);
96 struct resource_context *res_ctx,
99 struct resource_context *res_ctx,
102 struct resource_context *res_ctx,
141 …void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct dis…
/drivers/gpu/drm/amd/display/dc/inc/
A Dresource.h113 struct resource_context *res_ctx,
125 struct resource_context *res_ctx,
130 struct resource_context *res_ctx,
135 struct resource_context *res_ctx,
148 struct resource_context *res_ctx,
152 struct resource_context *res_ctx,
378 struct resource_context *res_ctx,
388 struct resource_context *res_ctx,
398 struct resource_context *res_ctx,
407 struct resource_context *res_ctx,
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/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c114 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_merge_pipes_for_subvp()
159 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_all_pipes_have_stream_and_plane()
176 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_in_use()
201 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_any_surfaces_rotated()
370 if (!context->res_ctx.pipe_ctx[i].stream) in dcn32_determine_det_override()
385 struct resource_context *res_ctx = &context->res_ctx; in dcn32_set_det_allocations() local
391 if (!res_ctx->pipe_ctx[i].stream) in dcn32_set_det_allocations()
394 pipe = &res_ctx->pipe_ctx[i]; in dcn32_set_det_allocations()
754 struct resource_context *res_ctx = &context->res_ctx; in dcn32_update_dml_pipes_odm_policy_based_on_context() local
760 if (!res_ctx->pipe_ctx[i].stream) in dcn32_update_dml_pipes_odm_policy_based_on_context()
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A Ddcn32_resource.c1596 struct resource_context *res_ctx, in dcn32_acquire_post_bldn_3dlut() argument
1618 struct resource_context *res_ctx, in dcn32_release_post_bldn_3dlut() argument
1868 struct resource_context *res_ctx = &context->res_ctx; in dcn32_populate_dml_pipes_from_context() local
1901 pipe = &res_ctx->pipe_ctx[i]; in dcn32_populate_dml_pipes_from_context()
1916 if (!res_ctx->pipe_ctx[i].stream) in dcn32_populate_dml_pipes_from_context()
1918 pipe = &res_ctx->pipe_ctx[i]; in dcn32_populate_dml_pipes_from_context()
2661 struct resource_context *res_ctx, in find_idle_secondary_pipe_check_mpo() argument
2728 struct resource_context *res_ctx = &state->res_ctx; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer() local
2809 &cur_ctx->res_ctx, &new_ctx->res_ctx, in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2838 &cur_ctx->res_ctx, &new_ctx->res_ctx, in dcn32_acquire_free_pipe_as_secondary_opp_head()
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/drivers/gpu/drm/amd/display/dc/dce/
A Ddmub_replay.c55 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_replay_enable() local
68 if (res_ctx && in dmub_replay_enable()
69 res_ctx->pipe_ctx[i].stream && in dmub_replay_enable()
70 res_ctx->pipe_ctx[i].stream->link && in dmub_replay_enable()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_replay_enable()
149 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_replay_copy_settings() local
153 if (res_ctx && in dmub_replay_copy_settings()
154 res_ctx->pipe_ctx[i].stream && in dmub_replay_copy_settings()
155 res_ctx->pipe_ctx[i].stream->link && in dmub_replay_copy_settings()
156 res_ctx->pipe_ctx[i].stream->link == link && in dmub_replay_copy_settings()
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/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1001 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_writeback_from_context()
1322 struct resource_context *res_ctx = &context->res_ctx; in dcn20_populate_dml_pipes_from_context() local
1327 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_pipes_from_context()
1335 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_pipes_from_context()
1340 res_ctx->pipe_ctx[pipe_cnt].stream, in dcn20_populate_dml_pipes_from_context()
1341 res_ctx->pipe_ctx[i].stream) && in dcn20_populate_dml_pipes_from_context()
1343 res_ctx->pipe_ctx[pipe_cnt].stream, in dcn20_populate_dml_pipes_from_context()
1344 res_ctx->pipe_ctx[i].stream))) { in dcn20_populate_dml_pipes_from_context()
1357 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_pipes_from_context()
1426 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state in dcn20_populate_dml_pipes_from_context()
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/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1326 struct resource_context *res_ctx, in dcn20_acquire_dsc() argument
1353 if (!res_ctx->is_dsc_acquired[i]) { in dcn20_acquire_dsc()
1355 res_ctx->is_dsc_acquired[i] = true; in dcn20_acquire_dsc()
1368 res_ctx->is_dsc_acquired[i] = false; in dcn20_release_dsc()
1418 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { in remove_dsc_from_stream_resource()
1480 struct resource_context *res_ctx, in dcn20_split_stream_for_odm() argument
1534 struct resource_context *res_ctx, in dcn20_split_stream_for_mpc() argument
1679 struct resource_context *res_ctx, in dcn20_find_secondary_pipe() argument
2058 dc, &context->res_ctx, in dcn20_fast_validate_bw()
2089 dc, &context->res_ctx, in dcn20_fast_validate_bw()
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A Ddcn20_resource.h132 void dcn20_release_dsc(struct resource_context *res_ctx,
137 struct resource_context *res_ctx,
143 struct resource_context *res_ctx,
147 struct resource_context *res_ctx,
151 struct resource_context *res_ctx,
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c488 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_set_phantom_stream_timing()
819 pipe = &context->res_ctx.pipe_ctx[i]; in subvp_drr_schedulable()
1182 &context->res_ctx, stream); in init_pipe_slice_table_from_context()
1190 &context->res_ctx, dpp_pipes); in init_pipe_slice_table_from_context()
1741 if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state && in dcn32_calculate_dlg_params()
1743 … context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) && in dcn32_calculate_dlg_params()
1800 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, in dcn32_calculate_dlg_params()
1853 struct resource_context *res_ctx, in dcn32_split_stream_for_mpc_or_odm() argument
2068 dc, &context->res_ctx, in dcn32_apply_merge_split_flags_helper()
2090 dc, &context->res_ctx, in dcn32_apply_merge_split_flags_helper()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c1523 &dc->current_state->res_ctx, in update_dsc_for_odm_change()
1650 &context->res_ctx, opp_heads); in dcn401_wait_for_det_buffer_update_under_otg_master()
1656 &context->res_ctx, in dcn401_wait_for_det_buffer_update_under_otg_master()
1681 pipe = &context->res_ctx.pipe_ctx[i]; in dcn401_interdependent_update_lock()
1693 pipe = &context->res_ctx.pipe_ctx[i]; in dcn401_interdependent_update_lock()
1715 pipe = &context->res_ctx.pipe_ctx[i]; in dcn401_interdependent_update_lock()
2092 pipe = &context->res_ctx.pipe_ctx[i]; in dcn401_program_front_end_for_ctx()
2122 &context->res_ctx.pipe_ctx[i]); in dcn401_program_front_end_for_ctx()
2183 pipe = &context->res_ctx.pipe_ctx[i]; in dcn401_program_front_end_for_ctx()
2196 pipe = &context->res_ctx.pipe_ctx[i]; in dcn401_program_front_end_for_ctx()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_utils.c118 …num_pipes = dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &context->res_ctx, dc… in dml21_find_dc_pipes_for_plane()
121 …ster_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream); in dml21_find_dc_pipes_for_plane()
123 …->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &context->res_ctx, dc_main_pipes); in dml21_find_dc_pipes_for_plane()
137 …dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, &context->res_ctx, dc_phantom_… in dml21_find_dc_pipes_for_plane()
201 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in is_sub_vp_enabled()
441 if (context->res_ctx.pipe_ctx[k].stream && in dml21_build_fams2_programming()
442 context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id && in dml21_build_fams2_programming()
443 context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) { in dml21_build_fams2_programming()
478 if (context->res_ctx.pipe_ctx[k].stream && in dml21_build_fams2_programming()
479 context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id && in dml21_build_fams2_programming()
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/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1325 struct resource_context *res_ctx = &context->res_ctx; in dcn30_populate_dml_pipes_from_context() local
1332 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1388 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1429 struct resource_context *res_ctx, in dcn30_acquire_post_bldn_3dlut() argument
1465 struct resource_context *res_ctx, in dcn30_release_post_bldn_3dlut() argument
1522 struct resource_context *res_ctx, in dcn30_split_stream_for_mpc_or_odm() argument
1600 pipe = &context->res_ctx.pipe_ctx[i]; in dcn30_find_split_pipe()
1615 pipe = &context->res_ctx.pipe_ctx[i]; in dcn30_find_split_pipe()
1802 dc, &context->res_ctx, in dcn30_internal_validate_bw()
1824 dc, &context->res_ctx, in dcn30_internal_validate_bw()
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A Ddcn30_resource.h76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
84 struct resource_context *res_ctx,
91 struct resource_context *res_ctx,
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c232 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; in dcn32_calculate_cab_allocation()
385 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
406 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
1250 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_resync_fifo_dccg_dio()
1272 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_resync_fifo_dccg_dio()
1522 if (context->res_ctx.is_dsc_acquired[i]) { in dcn32_update_dsc_pg()
1541 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn32_disable_phantom_streams()
1593 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn32_enable_phantom_streams()
1742 cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i]; in dcn32_is_pipe_topology_transition_seamless()
1743 new_pipe = &new_ctx->res_ctx.pipe_ctx[i]; in dcn32_is_pipe_topology_transition_seamless()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c2055 pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
2069 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn20_program_front_end_for_ctx()
2083 &context->res_ctx.pipe_ctx[i]); in dcn20_program_front_end_for_ctx()
2108 && !context->res_ctx.pipe_ctx[i].top_pipe in dcn20_program_front_end_for_ctx()
2110 && context->res_ctx.pipe_ctx[i].stream) in dcn20_program_front_end_for_ctx()
2137 &dc->current_state->res_ctx.pipe_ctx[i]); in dcn20_program_front_end_for_ctx()
2143 pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
2156 pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
2181 pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
2252 &dc->current_state->res_ctx.pipe_ctx[i]); in dcn20_post_unlock_program_front_end()
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/drivers/gpu/drm/amd/display/dc/hwss/dce60/
A Ddce60_hwseq.c56 struct resource_context *res_ctx = &context->res_ctx; in dce60_should_enable_fbc() local
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
396 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce60_apply_ctx_for_surface()
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c1810 &dc->current_state->res_ctx.pipe_ctx[i]); in disable_vga_and_power_gate_all_controllers()
2077 struct resource_context *res_ctx, in dce110_set_safe_displaymarks() argument
2089 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) in dce110_set_safe_displaymarks()
2093 res_ctx->pipe_ctx[i].plane_res.mi, in dce110_set_safe_displaymarks()
2102 res_ctx->pipe_ctx[i].plane_res.mi, in dce110_set_safe_displaymarks()
2198 struct resource_context *res_ctx = &context->res_ctx; in should_enable_fbc() local
2213 if (res_ctx->pipe_ctx[i].stream) { in should_enable_fbc()
2215 pipe_ctx = &res_ctx->pipe_ctx[i]; in should_enable_fbc()
2291 &dc->current_state->res_ctx.pipe_ctx[i]; in dce110_reset_hw_ctx_wrap()
2473 &dc->current_state->res_ctx.pipe_ctx[i]; in dce110_apply_ctx_to_hw()
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