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Searched refs:reset_lock (Results 1 – 25 of 28) sorted by relevance

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/drivers/clk/mmp/
A Dclk-of-pxa1928.c96 static DEFINE_SPINLOCK(reset_lock);
108 … "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
109 … "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
110 … "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
111 … "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
112 … "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI4 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
114 …O, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
117 …0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
118 …1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
119 …2, "pwm2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
[all …]
A Dclk-of-mmp2.c236 static DEFINE_SPINLOCK(reset_lock);
251 …_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
252 …_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
253 …_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
254 …_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
255 …_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
257 …MP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
260 …P2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
261 …P2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
262 …P2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
[all …]
A Dclk-of-pxa910.c125 static DEFINE_SPINLOCK(reset_lock);
141 …TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
142 …910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
145 …10_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
146 …10_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
147 …10_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
148 …10_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
159 …WSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
A Dclk-of-pxa168.c160 static DEFINE_SPINLOCK(reset_lock);
184 …168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x1, 0x1, 0x0, 0, &reset_lock},
/drivers/pci/hotplug/
A Dpciehp_pci.c71 up_read(&ctrl->reset_lock); in pciehp_configure_device()
73 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_configure_device()
123 up_read(&ctrl->reset_lock); in pciehp_unconfigure_device()
125 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_unconfigure_device()
A Dpciehp_hpc.c616 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_ignore_link_change()
619 up_read(&ctrl->reset_lock); in pciehp_ignore_link_change()
784 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_ist()
789 up_read(&ctrl->reset_lock); in pciehp_ist()
947 down_write_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_reset_slot()
955 up_write(&ctrl->reset_lock); in pciehp_reset_slot()
1034 init_rwsem(&ctrl->reset_lock); in pcie_init()
A Dpciehp_core.c170 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_check_presence()
181 up_read(&ctrl->reset_lock); in pciehp_check_presence()
A Dpciehp.h114 struct rw_semaphore reset_lock; member
/drivers/net/ethernet/xilinx/
A Dxilinx_emaclite.c129 spinlock_t reset_lock; /* serialize xmit and tx_timeout execution */ member
531 spin_lock_irqsave(&lp->reset_lock, flags); in xemaclite_tx_timeout()
550 spin_unlock_irqrestore(&lp->reset_lock, flags); in xemaclite_tx_timeout()
1008 spin_lock_irqsave(&lp->reset_lock, flags); in xemaclite_send()
1018 spin_unlock_irqrestore(&lp->reset_lock, flags); in xemaclite_send()
1021 spin_unlock_irqrestore(&lp->reset_lock, flags); in xemaclite_send()
1126 spin_lock_init(&lp->reset_lock); in xemaclite_of_probe()
/drivers/hid/i2c-hid/
A Di2c-hid-core.c111 struct mutex reset_lock; member
467 lockdep_assert_held(&ihid->reset_lock); in i2c_hid_start_hwreset()
700 mutex_lock(&ihid->reset_lock); in i2c_hid_output_raw_report()
716 mutex_unlock(&ihid->reset_lock); in i2c_hid_output_raw_report()
761 mutex_lock(&ihid->reset_lock); in i2c_hid_parse()
769 mutex_unlock(&ihid->reset_lock); in i2c_hid_parse()
1013 mutex_lock(&ihid->reset_lock); in i2c_hid_core_resume()
1017 mutex_unlock(&ihid->reset_lock); in i2c_hid_core_resume()
1239 mutex_init(&ihid->reset_lock); in i2c_hid_core_probe()
/drivers/net/ethernet/qualcomm/emac/
A Demac.c84 mutex_lock(&adpt->reset_lock); in emac_reinit_locked()
90 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked()
271 mutex_lock(&adpt->reset_lock); in emac_close()
279 mutex_unlock(&adpt->reset_lock); in emac_close()
626 mutex_init(&adpt->reset_lock); in emac_probe()
A Demac.h377 struct mutex reset_lock; member
/drivers/vfio/pci/virtio/
A Dmigrate.c258 spin_lock(&virtvdev->reset_lock); in virtiovf_state_mutex_unlock()
261 spin_unlock(&virtvdev->reset_lock); in virtiovf_state_mutex_unlock()
267 spin_unlock(&virtvdev->reset_lock); in virtiovf_state_mutex_unlock()
284 spin_lock(&virtvdev->reset_lock); in virtiovf_migration_reset_done()
287 spin_unlock(&virtvdev->reset_lock); in virtiovf_migration_reset_done()
290 spin_unlock(&virtvdev->reset_lock); in virtiovf_migration_reset_done()
1315 spin_lock_init(&virtvdev->reset_lock); in virtiovf_set_migratable()
A Dcommon.h100 spinlock_t reset_lock; member
/drivers/accel/ivpu/
A Divpu_pm.c129 down_write(&vdev->pm->reset_lock); in ivpu_pm_reset_begin()
148 up_write(&vdev->pm->reset_lock); in ivpu_pm_reset_complete()
401 init_rwsem(&pm->reset_lock); in ivpu_pm_init()
A Divpu_pm.h18 struct rw_semaphore reset_lock; member
A Divpu_job.c821 down_read(&vdev->pm->reset_lock); in ivpu_submit()
823 up_read(&vdev->pm->reset_lock); in ivpu_submit()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_reset.c111 mutex_lock(&tmp_adev->reset_cntl->reset_lock); in amdgpu_reset_xgmi_reset_on_init_perform_reset()
140 mutex_unlock(&tmp_adev->reset_cntl->reset_lock); in amdgpu_reset_xgmi_reset_on_init_perform_reset()
A Daldebaran.c168 mutex_lock(&tmp_adev->reset_cntl->reset_lock); in aldebaran_mode2_perform_reset()
204 mutex_unlock(&tmp_adev->reset_cntl->reset_lock); in aldebaran_mode2_perform_reset()
A Damdgpu_reset.h77 struct mutex reset_lock; member
/drivers/vfio/pci/mlx5/
A Dmain.c1201 spin_lock(&mvdev->reset_lock); in mlx5vf_state_mutex_unlock()
1204 spin_unlock(&mvdev->reset_lock); in mlx5vf_state_mutex_unlock()
1210 spin_unlock(&mvdev->reset_lock); in mlx5vf_state_mutex_unlock()
1289 spin_lock(&mvdev->reset_lock); in mlx5vf_pci_aer_reset_done()
1292 spin_unlock(&mvdev->reset_lock); in mlx5vf_pci_aer_reset_done()
1295 spin_unlock(&mvdev->reset_lock); in mlx5vf_pci_aer_reset_done()
A Dcmd.h182 spinlock_t reset_lock; member
/drivers/gpu/drm/v3d/
A Dv3d_gem.c281 ret = drmm_mutex_init(dev, &v3d->reset_lock); in v3d_gem_init()
A Dv3d_sched.c726 mutex_lock(&v3d->reset_lock); in v3d_gpu_reset_for_timeout()
746 mutex_unlock(&v3d->reset_lock); in v3d_gpu_reset_for_timeout()
A Dv3d_drv.h184 struct mutex reset_lock; member

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