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Searched refs:reset_reg (Results 1 – 24 of 24) sorted by relevance

/drivers/acpi/acpica/
A Dhwxface.c34 struct acpi_generic_address *reset_reg; in acpi_reset() local
39 reset_reg = &acpi_gbl_FADT.reset_register; in acpi_reset()
44 !reset_reg->address) { in acpi_reset()
48 if (reset_reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { in acpi_reset()
60 status = acpi_os_write_port((acpi_io_address)reset_reg->address, in acpi_reset()
66 status = acpi_hw_write(acpi_gbl_FADT.reset_value, reset_reg); in acpi_reset()
/drivers/reset/
A Dreset-rzv2h-usb2phy.c27 u16 reset_reg; member
59 writel(data->reset_assert_val, priv->base + data->reset_reg); in rzv2h_usbphy_assert_helper()
100 writel(data->reset_deassert_val, priv->base + data->reset_reg); in rzv2h_usbphy_reset_deassert()
102 writel(data->reset_release_val, priv->base + data->reset_reg); in rzv2h_usbphy_reset_deassert()
124 reg = readl(priv->base + priv->data->reset_reg); in rzv2h_usbphy_reset_status()
209 .reset_reg = 0,
A Dreset-microchip-sparx5.c21 u32 reset_reg; member
47 regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, in sparx5_switch_reset()
51 return regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val, in sparx5_switch_reset()
183 .reset_reg = 0x0,
190 .reset_reg = 0x0,
/drivers/leds/
A Dleds-is31fl32xx.c78 u8 reset_reg; member
92 .reset_reg = 0x4f,
103 .reset_reg = 0x4f,
114 .reset_reg = 0x17,
128 .reset_reg = IS31FL32XX_REG_NONE,
253 if (cdef->reset_reg != IS31FL32XX_REG_NONE) { in is31fl32xx_reset_regs()
254 ret = is31fl32xx_write(priv, cdef->reset_reg, 0); in is31fl32xx_reset_regs()
A Dleds-lp50xx.c191 u8 reset_reg; member
203 .reset_reg = LP5012_RESET,
214 .reset_reg = LP5012_RESET,
225 .reset_reg = LP5024_RESET,
236 .reset_reg = LP5024_RESET,
247 .reset_reg = LP5036_RESET,
258 .reset_reg = LP5036_RESET,
371 return regmap_write(priv->regmap, priv->chip_info->reset_reg, LP50XX_SW_RESET); in lp50xx_reset()
A Dleds-is31fl319x.c107 u8 reset_reg; member
309 .reset_reg = IS31FL3190_RESET,
320 .reset_reg = IS31FL3190_RESET,
331 .reset_reg = IS31FL3196_RESET,
342 .reset_reg = IS31FL3196_RESET,
529 err = regmap_write(is31->regmap, is31->cdef->reset_reg, 0x00); in is31fl319x_probe()
/drivers/net/ethernet/intel/idpf/
A Didpf_dev.c136 adapter->reset_reg.rstat = idpf_get_rstat_reg_addr(adapter, PFGEN_RSTAT); in idpf_reset_reg_init()
137 adapter->reset_reg.rstat_m = PFGEN_RSTAT_PFR_STATE_M; in idpf_reset_reg_init()
148 u32 reset_reg; in idpf_trigger_reset() local
150 reset_reg = readl(idpf_get_rstat_reg_addr(adapter, PFGEN_CTRL)); in idpf_trigger_reset()
151 writel(reset_reg | PFGEN_CTRL_PFSWR, in idpf_trigger_reset()
A Didpf_vf_dev.c135 adapter->reset_reg.rstat = idpf_get_rstat_reg_addr(adapter, VFGEN_RSTAT); in idpf_vf_reset_reg_init()
136 adapter->reset_reg.rstat_m = VFGEN_RSTAT_VFR_STATE_M; in idpf_vf_reset_reg_init()
A Didpf_lib.c1729 struct idpf_reset_reg *reset_reg) in idpf_check_reset_complete() argument
1735 u32 reg_val = readl(reset_reg->rstat); in idpf_check_reset_complete()
1741 if (reg_val != 0xFFFFFFFF && (reg_val & reset_reg->rstat_m)) in idpf_check_reset_complete()
1827 err = idpf_check_reset_complete(&adapter->hw, &adapter->reset_reg); in idpf_init_hard_reset()
A Didpf.h614 struct idpf_reset_reg reset_reg; member
/drivers/clk/meson/
A Dmeson-aoclk.h23 const unsigned int reset_reg; member
A Dmeson-aoclk.c29 return regmap_write(rstc->regmap, rstc->data->reset_reg, in meson_aoclk_do_reset()
A Dgxbb-aoclk.c258 .reset_reg = AO_RTI_GEN_CNTL_REG0,
A Daxg-aoclk.c294 .reset_reg = AO_RTI_GEN_CNTL_REG0,
A Dg12a-aoclk.c417 .reset_reg = AO_RTI_GEN_CNTL_REG0,
/drivers/clk/qcom/
A Dclk-rcg.c479 unsigned int reset_reg; in __clk_rcg_set_rate() local
482 reset_reg = rcg->clkr.enable_reg; in __clk_rcg_set_rate()
484 reset_reg = rcg->ns_reg; in __clk_rcg_set_rate()
488 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask); in __clk_rcg_set_rate()
511 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0); in __clk_rcg_set_rate()
/drivers/clk/tegra/
A Dclk-pll.c368 if (pll->params->reset_reg) { in _clk_pll_enable()
369 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_enable()
371 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_enable()
406 if (pll->params->reset_reg) { in _clk_pll_disable()
407 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_disable()
409 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_disable()
A Dclk.h315 u32 reset_reg; member
A Dclk-tegra210.c1717 .reset_reg = PLLC_MISC0,
1754 .reset_reg = PLLC2_MISC0,
1786 .reset_reg = PLLC3_MISC0,
2076 .reset_reg = PLLA1_MISC0,
/drivers/net/ethernet/qlogic/qed/
A Dqed_debug.c1473 const struct dbg_reset_reg *reset_reg; in qed_bus_reset_dbg_block() local
1477 reset_reg = qed_get_dbg_reset_reg(p_hwfn, block->reset_reg_id); in qed_bus_reset_dbg_block()
1479 DWORDS_TO_BYTES(GET_FIELD(reset_reg->data, DBG_RESET_REG_ADDR)); in qed_bus_reset_dbg_block()
1738 const struct dbg_reset_reg *reset_reg; in qed_grc_unreset_blocks() local
1741 reset_reg = qed_get_dbg_reset_reg(p_hwfn, reset_reg_id); in qed_grc_unreset_blocks()
1744 (reset_reg->data, DBG_RESET_REG_IS_REMOVED)) in qed_grc_unreset_blocks()
1749 GET_FIELD(reset_reg->data, in qed_grc_unreset_blocks()
2391 const struct dbg_reset_reg *reset_reg; in qed_grc_dump_reset_regs() local
2394 reset_reg = qed_get_dbg_reset_reg(p_hwfn, reset_reg_id); in qed_grc_dump_reset_regs()
2396 if (GET_FIELD(reset_reg->data, DBG_RESET_REG_IS_REMOVED)) in qed_grc_dump_reset_regs()
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/drivers/media/dvb-frontends/
A Ddib9000.c501 u16 reset_reg; in dib9000_mbx_host_init() local
514 reset_reg = dib9000_read_word(state, 1027 + mbox_offs); in dib9000_mbx_host_init()
516 } while ((reset_reg & 0x8000) && --tries); in dib9000_mbx_host_init()
518 if (reset_reg & 0x8000) { in dib9000_mbx_host_init()
/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_main.c10407 u8 port, u32 reset_reg, in bnx2x_prev_unload_close_umac() argument
10413 if (!(mask & reset_reg)) in bnx2x_prev_unload_close_umac()
10428 u32 val, base_addr, offset, mask, reset_reg; in bnx2x_prev_unload_close_mac() local
10435 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_prev_unload_close_mac()
10440 if ((mask & reset_reg) && val) { in bnx2x_prev_unload_close_mac()
10469 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { in bnx2x_prev_unload_close_mac()
10484 reset_reg, vals); in bnx2x_prev_unload_close_mac()
10486 reset_reg, vals); in bnx2x_prev_unload_close_mac()
10758 u32 reset_reg, tmp_reg = 0, rc; in bnx2x_prev_unload_common() local
10773 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); in bnx2x_prev_unload_common()
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/drivers/scsi/smartpqi/
A Dsmartpqi_init.c7649 union pqi_reset_register reset_reg; in pqi_wait_for_pqi_reset_completion() local
7657 reset_reg.all_bits = readl(&pqi_registers->device_reset); in pqi_wait_for_pqi_reset_completion()
7658 if (reset_reg.bits.reset_action == PQI_RESET_ACTION_COMPLETED) in pqi_wait_for_pqi_reset_completion()
7676 union pqi_reset_register reset_reg; in pqi_reset() local
7687 reset_reg.all_bits = 0; in pqi_reset()
7688 reset_reg.bits.reset_type = PQI_RESET_TYPE_HARD_RESET; in pqi_reset()
7689 reset_reg.bits.reset_action = PQI_RESET_ACTION_RESET; in pqi_reset()
7691 writel(reset_reg.all_bits, &ctrl_info->pqi_registers->device_reset); in pqi_reset()
/drivers/net/ethernet/broadcom/bnxt/
A Dbnxt.c10027 le32_to_cpu(resp->reset_reg[i]); in bnxt_hwrm_error_recovery_qcfg()

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