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Searched refs:resets (Results 1 – 25 of 237) sorted by relevance

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/drivers/usb/dwc3/
A Ddwc3-of-simple.c29 struct reset_control *resets; member
55 simple->resets = of_reset_control_array_get_optional_exclusive(np); in dwc3_of_simple_probe()
56 if (IS_ERR(simple->resets)) { in dwc3_of_simple_probe()
57 ret = PTR_ERR(simple->resets); in dwc3_of_simple_probe()
62 ret = reset_control_deassert(simple->resets); in dwc3_of_simple_probe()
90 reset_control_assert(simple->resets); in dwc3_of_simple_probe()
93 reset_control_put(simple->resets); in dwc3_of_simple_probe()
105 reset_control_assert(simple->resets); in __dwc3_of_simple_teardown()
107 reset_control_put(simple->resets); in __dwc3_of_simple_teardown()
149 reset_control_assert(simple->resets); in dwc3_of_simple_suspend()
[all …]
A Ddwc3-qcom-legacy.c79 struct reset_control *resets; member
749 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); in dwc3_qcom_probe()
750 if (IS_ERR(qcom->resets)) { in dwc3_qcom_probe()
751 return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), in dwc3_qcom_probe()
755 ret = reset_control_assert(qcom->resets); in dwc3_qcom_probe()
763 ret = reset_control_deassert(qcom->resets); in dwc3_qcom_probe()
839 reset_control_assert(qcom->resets); in dwc3_qcom_probe()
860 reset_control_assert(qcom->resets); in dwc3_qcom_remove()
/drivers/reset/
A Dcore.c244 rstc = resets->rstc[i]; in reset_control_array_rearm()
262 rstc = resets->rstc[i]; in reset_control_array_rearm()
1197 kfree(resets); in reset_control_array_put()
1425 struct reset_control_array *resets; in of_reset_control_array_get() local
1433 resets = kzalloc(struct_size(resets, rstc, num), GFP_KERNEL); in of_reset_control_array_get()
1434 if (!resets) in of_reset_control_array_get()
1436 resets->num_rstcs = num; in of_reset_control_array_get()
1442 resets->rstc[i] = rstc; in of_reset_control_array_get()
1444 resets->base.array = true; in of_reset_control_array_get()
1446 return &resets->base; in of_reset_control_array_get()
[all …]
A Dreset-qcom-pdc.c22 const struct qcom_pdc_reset_map *resets; member
56 .resets = sdm845_pdc_resets,
77 .resets = sc7280_pdc_resets,
92 u32 mask = BIT(data->desc->resets[idx].bit); in qcom_pdc_control_assert()
101 u32 mask = BIT(data->desc->resets[idx].bit); in qcom_pdc_control_deassert()
A Dreset-qcom-aoss.c19 const struct qcom_aoss_reset_map *resets; member
40 .resets = sdm845_aoss_resets,
54 const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; in qcom_aoss_control_assert()
66 const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; in qcom_aoss_control_deassert()
/drivers/phy/
A Dphy-lgm-usb.c41 struct reset_control *resets[ARRAY_SIZE(PHY_RESETS)]; member
78 reset_control_deassert(ta->resets[i]); in phy_init()
115 reset_control_assert(ta->resets[i]); in phy_shutdown()
189 struct reset_control *resets[ARRAY_SIZE(CTL_RESETS)]; in phy_probe() local
222 if (IS_ERR(resets[i])) { in phy_probe()
224 return PTR_ERR(resets[i]); in phy_probe()
230 if (IS_ERR(ta->resets[i])) { in phy_probe()
232 return PTR_ERR(ta->resets[i]); in phy_probe()
237 reset_control_assert(resets[i]); in phy_probe()
240 reset_control_assert(ta->resets[i]); in phy_probe()
[all …]
/drivers/gpu/drm/tegra/
A Dgr2d.c36 struct reset_control_bulk_data resets[RST_GR2D_MAX]; member
217 gr2d->resets[RST_MC].id = "mc"; in gr2d_get_resets()
218 gr2d->resets[RST_GR2D].id = "2d"; in gr2d_get_resets()
222 dev, gr2d->nresets, gr2d->resets); in gr2d_get_resets()
228 if (WARN_ON(!gr2d->resets[RST_GR2D].rstc)) in gr2d_get_resets()
306 reset_control_bulk_release(gr2d->nresets, gr2d->resets); in gr2d_runtime_suspend()
320 err = reset_control_acquire(gr2d->resets[RST_MC].rstc); in gr2d_runtime_suspend()
326 err = reset_control_assert(gr2d->resets[RST_MC].rstc); in gr2d_runtime_suspend()
327 reset_control_release(gr2d->resets[RST_MC].rstc); in gr2d_runtime_suspend()
338 reset_control_bulk_acquire(gr2d->nresets, gr2d->resets); in gr2d_runtime_suspend()
[all …]
A Dgr3d.c47 struct reset_control_bulk_data resets[RST_GR3D_MAX]; member
443 gr3d->resets[RST_MC].id = "mc"; in gr3d_get_resets()
444 gr3d->resets[RST_MC2].id = "mc2"; in gr3d_get_resets()
445 gr3d->resets[RST_GR3D].id = "3d"; in gr3d_get_resets()
446 gr3d->resets[RST_GR3D2].id = "3d2"; in gr3d_get_resets()
450 dev, gr3d->nresets, gr3d->resets); in gr3d_get_resets()
456 if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) || in gr3d_get_resets()
538 err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets); in gr3d_runtime_suspend()
553 reset_control_bulk_release(gr3d->nresets, gr3d->resets); in gr3d_runtime_suspend()
563 err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets); in gr3d_runtime_resume()
[all …]
/drivers/clk/visconti/
A Dreset.c26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
65 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_status()
88 const struct visconti_reset_data *resets, in visconti_register_reset_controller() argument
100 reset->resets = resets; in visconti_register_reset_controller()
A Dreset.h24 const struct visconti_reset_data *resets; member
32 const struct visconti_reset_data *resets,
/drivers/phy/qualcomm/
A Dphy-qcom-uniphy-pcie-28lp.c71 struct reset_control *resets; member
164 return reset_control_assert(phy->resets); in qcom_uniphy_pcie_power_off()
172 ret = reset_control_assert(phy->resets); in qcom_uniphy_pcie_power_on()
180 ret = reset_control_deassert(phy->resets); in qcom_uniphy_pcie_power_on()
214 phy->resets = devm_reset_control_array_get_exclusive(phy->dev); in qcom_uniphy_pcie_get_resources()
215 if (IS_ERR(phy->resets)) in qcom_uniphy_pcie_get_resources()
216 return PTR_ERR(phy->resets); in qcom_uniphy_pcie_get_resources()
A Dphy-qcom-qmp-pcie-msm8996.c212 struct reset_control_bulk_data *resets; member
328 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_com_init()
334 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_com_init()
352 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_com_init()
381 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_com_exit()
551 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_msm8996_reset_init()
552 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_msm8996_reset_init()
553 if (!qmp->resets) in qmp_pcie_msm8996_reset_init()
557 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_msm8996_reset_init()
559 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_reset_init()
/drivers/usb/cdns3/
A Dcdns3-starfive.c38 struct reset_control *resets; member
88 ret = reset_control_deassert(data->resets); in cdns_clk_rst_init()
103 reset_control_assert(data->resets); in cdns_clk_rst_deinit()
135 data->resets = devm_reset_control_array_get_exclusive(data->dev); in cdns_starfive_probe()
136 if (IS_ERR(data->resets)) in cdns_starfive_probe()
137 return dev_err_probe(data->dev, PTR_ERR(data->resets), in cdns_starfive_probe()
/drivers/clk/sunxi-ng/
A Dccu-sun8i-de2.c189 .resets = sun8i_a83t_de2_resets,
199 .resets = sun8i_h3_de2_resets,
209 .resets = sun8i_a83t_de2_resets,
219 .resets = sun8i_a83t_de2_resets,
229 .resets = sun50i_a64_de2_resets,
239 .resets = sun50i_h5_de2_resets,
249 .resets = sun50i_h5_de2_resets,
/drivers/usb/host/
A Dohci-platform.c41 struct reset_control *resets; member
157 priv->resets = devm_reset_control_array_get_optional_shared( in ohci_platform_probe()
159 if (IS_ERR(priv->resets)) { in ohci_platform_probe()
160 err = PTR_ERR(priv->resets); in ohci_platform_probe()
164 err = reset_control_deassert(priv->resets); in ohci_platform_probe()
228 reset_control_assert(priv->resets); in ohci_platform_probe()
254 reset_control_assert(priv->resets); in ohci_platform_remove()
/drivers/pci/controller/dwc/
A Dpcie-qcom.c447 res->resets[0].id = "pci"; in qcom_pcie_get_resources_2_1_0()
448 res->resets[1].id = "axi"; in qcom_pcie_get_resources_2_1_0()
449 res->resets[2].id = "ahb"; in qcom_pcie_get_resources_2_1_0()
450 res->resets[3].id = "por"; in qcom_pcie_get_resources_2_1_0()
451 res->resets[4].id = "phy"; in qcom_pcie_get_resources_2_1_0()
452 res->resets[5].id = "ext"; in qcom_pcie_get_resources_2_1_0()
756 res->resets[4].id = "pwr"; in qcom_pcie_get_resources_2_4_0()
757 res->resets[5].id = "ahb"; in qcom_pcie_get_resources_2_4_0()
758 res->resets[6].id = "pipe"; in qcom_pcie_get_resources_2_4_0()
761 res->resets[9].id = "parf"; in qcom_pcie_get_resources_2_4_0()
[all …]
/drivers/spi/
A Dspi-rzv2h-rspi.c73 struct reset_control_bulk_data resets[RSPI_RESET_NUM]; member
385 rspi->resets[0].id = "presetn"; in rzv2h_rspi_probe()
386 rspi->resets[1].id = "tresetn"; in rzv2h_rspi_probe()
388 rspi->resets); in rzv2h_rspi_probe()
396 ret = reset_control_bulk_deassert(RSPI_RESET_NUM, rspi->resets); in rzv2h_rspi_probe()
434 reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets); in rzv2h_rspi_probe()
445 reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets); in rzv2h_rspi_remove()
/drivers/media/platform/qcom/iris/
A Diris_probe.c95 struct reset_control_bulk_data **resets, in iris_init_reset_table() argument
100 *resets = devm_kzalloc(core->dev, in iris_init_reset_table()
103 if (!*resets) in iris_init_reset_table()
107 (*resets)[i].id = rst_tbl[i]; in iris_init_reset_table()
109 return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, *resets); in iris_init_reset_table()
116 ret = iris_init_reset_table(core, &core->resets, in iris_init_resets()
/drivers/iio/adc/
A Drzg2l_adc.c538 struct reset_control_bulk_data resets[] = { in rzg2l_adc_suspend() local
553 ret = reset_control_bulk_assert(ARRAY_SIZE(resets), resets); in rzg2l_adc_suspend()
570 struct reset_control_bulk_data resets[] = { in rzg2l_adc_resume() local
576 ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); in rzg2l_adc_resume()
598 reset_control_bulk_assert(ARRAY_SIZE(resets), resets); in rzg2l_adc_resume()
/drivers/pci/controller/plda/
A Dpcie-starfive.c55 struct reset_control *resets; member
115 pcie->resets = devm_reset_control_array_get_exclusive(dev); in starfive_pcie_parse_dt()
116 if (IS_ERR(pcie->resets)) in starfive_pcie_parse_dt()
117 return dev_err_probe(dev, PTR_ERR(pcie->resets), in starfive_pcie_parse_dt()
180 ret = reset_control_deassert(pcie->resets); in starfive_pcie_clk_rst_init()
191 reset_control_assert(pcie->resets); in starfive_pcie_clk_rst_deinit()
/drivers/media/platform/chips-media/wave5/
A Dwave5-vpu.c230 dev->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev); in wave5_vpu_probe()
231 if (IS_ERR(dev->resets)) { in wave5_vpu_probe()
232 return dev_err_probe(&pdev->dev, PTR_ERR(dev->resets), in wave5_vpu_probe()
236 ret = reset_control_deassert(dev->resets); in wave5_vpu_probe()
345 reset_control_assert(dev->resets); in wave5_vpu_probe()
364 reset_control_assert(dev->resets); in wave5_vpu_remove()
/drivers/gpu/host1x/
A Ddev.c500 host->resets[0].id = "mc"; in host1x_get_resets()
501 host->resets[1].id = "host1x"; in host1x_get_resets()
502 host->nresets = ARRAY_SIZE(host->resets); in host1x_get_resets()
505 host->dev, host->nresets, host->resets); in host1x_get_resets()
708 err = reset_control_bulk_assert(host->nresets, host->resets); in host1x_runtime_suspend()
718 reset_control_bulk_release(host->nresets, host->resets); in host1x_runtime_suspend()
735 err = reset_control_bulk_acquire(host->nresets, host->resets); in host1x_runtime_resume()
747 err = reset_control_bulk_deassert(host->nresets, host->resets); in host1x_runtime_resume()
762 reset_control_bulk_release(host->nresets, host->resets); in host1x_runtime_resume()
/drivers/clk/renesas/
A Drzv2h-cpg.c92 struct rzv2h_reset *resets; member
863 unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index); in __rzv2h_cpg_assert()
864 u32 mask = BIT(priv->resets[id].reset_bit); in __rzv2h_cpg_assert()
865 u8 monbit = priv->resets[id].mon_bit; in __rzv2h_cpg_assert()
875 reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index); in __rzv2h_cpg_assert()
912 u8 monbit = priv->resets[id].mon_bit; in rzv2h_cpg_status()
934 if (rst_index == priv->resets[i].reset_index && in rzv2h_cpg_reset_xlate()
935 rst_bit == priv->resets[i].reset_bit) in rzv2h_cpg_reset_xlate()
1123 priv->resets = devm_kmemdup_array(dev, info->resets, info->num_resets, in rzv2h_cpg_probe()
1124 sizeof(*info->resets), GFP_KERNEL); in rzv2h_cpg_probe()
[all …]
/drivers/clk/qcom/
A Dlpasscc-sc8280xp.c36 .resets = lpass_audiocc_sc8280xp_resets,
54 .resets = lpasscc_sc8280xp_resets,
A Dlpasscc-sm6115.c33 .resets = lpass_audiocc_sm6115_resets,
51 .resets = lpasscc_sm6115_resets,

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