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Searched refs:round_rate (Results 1 – 25 of 167) sorted by relevance

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/drivers/clk/imx/
A Dclk-pllv4.c103 unsigned long round_rate, i; in clk_pllv4_determine_rate() local
115 round_rate = parent_rate * mult; in clk_pllv4_determine_rate()
120 round_rate = parent_rate * pllv4_mult_table[i]; in clk_pllv4_determine_rate()
121 if (req->rate >= round_rate) { in clk_pllv4_determine_rate()
139 temp64 = (u64)(req->rate - round_rate); in clk_pllv4_determine_rate()
151 req->rate = round_rate; in clk_pllv4_determine_rate()
160 req->rate = round_rate + (u32)temp64; in clk_pllv4_determine_rate()
/drivers/clk/
A Dclk-vt8500.c205 .round_rate = vt8500_dclk_round_rate,
214 .round_rate = vt8500_dclk_round_rate,
602 long round_rate; in vtwm_pll_round_rate() local
609 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1); in vtwm_pll_round_rate()
614 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()
619 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()
624 round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()
633 return round_rate; in vtwm_pll_round_rate()
668 .round_rate = vtwm_pll_round_rate,
A Dclk-composite.c58 rate = rate_ops->round_rate(rate_hw, req->rate, in clk_composite_determine_rate_for_parent()
83 (rate_ops->determine_rate || rate_ops->round_rate) && in clk_composite_determine_rate()
162 return rate_ops->round_rate(rate_hw, rate, prate); in clk_composite_round_rate()
291 else if (rate_ops->round_rate) in __clk_hw_register_composite()
292 clk_composite_ops->round_rate = in __clk_hw_register_composite()
297 if (rate_ops->determine_rate || rate_ops->round_rate) in __clk_hw_register_composite()
A Dclk-scpi.c57 .round_rate = scpi_clk_round_rate,
127 .round_rate = scpi_dvfs_round_rate,
A Dclk-highbank.c188 .round_rate = clk_pll_round_rate,
258 .round_rate = clk_periclk_round_rate,
/drivers/clk/ti/
A Ddpll.c28 .round_rate = &omap4_dpll_regm4xen_round_rate,
51 .round_rate = &omap2_dpll_round_rate,
64 .round_rate = &omap2_dpll_round_rate,
83 .round_rate = &omap2_dpll_round_rate,
94 .round_rate = &omap2_dpll_round_rate,
106 .round_rate = &omap2_dpll_round_rate,
118 .round_rate = &omap2_dpll_round_rate,
130 .round_rate = &omap2_dpll_round_rate,
/drivers/gpu/drm/bridge/imx/
A Dimx8mp-hdmi-tx.c26 long round_rate; in imx8mp_hdmi_mode_valid() local
34 round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000); in imx8mp_hdmi_mode_valid()
41 if (abs(round_rate - mode->clock * 1000) > mode->clock * 5) in imx8mp_hdmi_mode_valid()
/drivers/sh/clk/
A Dcpg.c186 .round_rate = sh_clk_div_round_rate,
192 .round_rate = sh_clk_div_round_rate,
317 .round_rate = sh_clk_div_round_rate,
371 .round_rate = sh_clk_div_round_rate,
449 .round_rate = fsidiv_round_rate,
/drivers/clk/mvebu/
A Dclk-corediv.c202 .round_rate = clk_corediv_round_rate,
218 .round_rate = clk_corediv_round_rate,
231 .round_rate = clk_corediv_round_rate,
243 .round_rate = clk_corediv_round_rate,
/drivers/clk/qcom/
A Dclk-alpha-pll.c1178 .round_rate = clk_alpha_pll_round_rate,
1198 .round_rate = clk_alpha_pll_round_rate,
1208 .round_rate = clk_alpha_pll_round_rate,
1545 .round_rate = clk_alpha_pll_round_rate,
1554 .round_rate = clk_alpha_pll_round_rate,
1836 .round_rate = clk_alpha_pll_round_rate,
1847 .round_rate = clk_alpha_pll_round_rate,
1906 .round_rate = clk_alpha_pll_round_rate,
2122 .round_rate = clk_alpha_pll_round_rate,
2132 .round_rate = clk_alpha_pll_round_rate,
[all …]
A Dclk-regmap-divider.c73 .round_rate = div_round_rate,
80 .round_rate = div_round_ro_rate,
/drivers/clk/mxs/
A Dclk-div.c48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
66 .round_rate = clk_div_round_rate,
/drivers/clk/ux500/
A Dclk-prcmu.c160 .round_rate = clk_prcmu_round_rate,
172 .round_rate = clk_prcmu_round_rate,
190 .round_rate = clk_prcmu_round_rate,
/drivers/clk/samsung/
A Dclk-pll.c301 .round_rate = samsung_pll_round_rate,
414 .round_rate = samsung_pll_round_rate,
517 .round_rate = samsung_pll_round_rate,
615 .round_rate = samsung_pll_round_rate,
738 .round_rate = samsung_pll_round_rate,
883 .round_rate = samsung_pll_round_rate,
1096 .round_rate = samsung_pll_round_rate,
1188 .round_rate = samsung_pll_round_rate,
1280 .round_rate = samsung_pll_round_rate,
/drivers/clk/actions/
A Dowl-composite.c131 return comp->fix_fact_ops->round_rate(&fix_fact_hw->hw, rate, parent_rate); in owl_comp_fix_fact_round_rate()
196 .round_rate = owl_comp_fix_fact_round_rate,
/drivers/media/platform/qcom/camss/
A Dcamss-csiphy.c157 long round_rate; in csiphy_set_clock_rates() local
176 round_rate = clk_round_rate(clock->clk, clock->freq[j]); in csiphy_set_clock_rates()
177 if (round_rate < 0) { in csiphy_set_clock_rates()
179 round_rate); in csiphy_set_clock_rates()
183 csiphy->timer_clk_rate = round_rate; in csiphy_set_clock_rates()
/drivers/clk/at91/
A Dclk-sam9x60-pll.c324 .round_rate = sam9x60_frac_pll_round_rate,
335 .round_rate = sam9x60_frac_pll_round_rate,
604 .round_rate = sam9x60_div_pll_round_rate,
615 .round_rate = sam9x60_div_pll_round_rate,
626 .round_rate = sam9x60_div_pll_round_rate,
/drivers/clk/baikal-t1/
A Dccu-div.c537 .round_rate = ccu_div_var_round_rate,
544 .round_rate = ccu_div_var_round_rate,
554 .round_rate = ccu_div_fixed_round_rate,
568 .round_rate = ccu_div_fixed_round_rate,
/drivers/clk/zynqmp/
A Ddivider.c202 .round_rate = zynqmp_clk_divider_round_rate,
208 .round_rate = zynqmp_clk_divider_round_rate,
/drivers/clk/spacemit/
A Dccu_mix.c201 .round_rate = ccu_factor_round_rate,
223 .round_rate = ccu_factor_round_rate,
A Dccu_ddn.c81 .round_rate = ccu_ddn_round_rate,
/drivers/clk/sifive/
A Dfu540-prci.h52 .round_rate = sifive_prci_wrpll_round_rate,
/drivers/clk/tegra/
A Dclk-audio-sync.c41 .round_rate = clk_sync_source_round_rate,
/drivers/clk/spear/
A Dclk-vco-pll.c167 .round_rate = clk_pll_round_rate,
268 .round_rate = clk_vco_round_rate,
/drivers/clk/sprd/
A Ddiv.c78 .round_rate = sprd_div_round_rate,

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