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Searched refs:rps (Results 1 – 25 of 53) sorted by relevance

123

/drivers/gpu/drm/i915/gt/
A Dintel_rps.c199 rps->pm_events, rps_pm_mask(rps, rps->last_freq)); in rps_enable_interrupts()
1192 rps->max_freq = rps->rp0_freq; in gen6_rps_init()
1709 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); in vlv_rps_init()
1717 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); in vlv_rps_init()
1721 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); in vlv_rps_init()
1743 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); in chv_rps_init()
1751 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); in chv_rps_init()
1755 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); in chv_rps_init()
2824 rps = &to_gt(i915)->rps; in i915_gpu_raise()
2851 rps = &to_gt(i915)->rps; in i915_gpu_lower()
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A Dintel_rps.h18 void intel_rps_init_early(struct intel_rps *rps);
19 void intel_rps_init(struct intel_rps *rps);
20 void intel_rps_sanitize(struct intel_rps *rps);
25 void intel_rps_enable(struct intel_rps *rps);
26 void intel_rps_disable(struct intel_rps *rps);
28 void intel_rps_park(struct intel_rps *rps);
29 void intel_rps_unpark(struct intel_rps *rps);
78 set_bit(INTEL_RPS_ENABLED, &rps->flags); in intel_rps_set_enabled()
93 set_bit(INTEL_RPS_ACTIVE, &rps->flags); in intel_rps_set_active()
123 set_bit(INTEL_RPS_TIMER, &rps->flags); in intel_rps_set_timer()
[all …]
A Dselftest_rps.c222 struct intel_rps *rps = &gt->rps; in live_rps_clock_interval() local
375 struct intel_rps *rps = &gt->rps; in live_rps_control() local
435 if (rps_set_check(rps, rps->min_freq) != rps->min_freq) { in live_rps_control()
452 if (rps_set_check(rps, rps->min_freq) != rps->min_freq) { in live_rps_control()
475 rps->min_freq, intel_gpu_freq(rps, rps->min_freq), in live_rps_control()
476 rps->max_freq, intel_gpu_freq(rps, rps->max_freq), in live_rps_control()
608 struct intel_rps *rps = &gt->rps; in live_rps_frequency_cs() local
747 struct intel_rps *rps = &gt->rps; in live_rps_frequency_srm() local
1024 struct intel_rps *rps = &gt->rps; in live_rps_interrupt() local
1136 struct intel_rps *rps = &gt->rps; in live_rps_power() local
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A Dintel_gt_pm_debugfs.c343 struct intel_rps *rps = &gt->rps; in intel_gt_pm_frequency_dump() local
379 intel_gpu_freq(rps, rps->cur_freq)); in intel_gt_pm_frequency_dump()
382 intel_gpu_freq(rps, rps->max_freq)); in intel_gt_pm_frequency_dump()
385 intel_gpu_freq(rps, rps->min_freq)); in intel_gt_pm_frequency_dump()
388 intel_gpu_freq(rps, rps->idle_freq)); in intel_gt_pm_frequency_dump()
417 struct intel_rps *rps = &gt->rps; in llc_show() local
482 struct intel_rps *rps = &gt->rps; in rps_boost_show() local
495 intel_gpu_freq(rps, rps->cur_freq), in rps_boost_show()
498 intel_gpu_freq(rps, rps->min_freq), in rps_boost_show()
501 intel_gpu_freq(rps, rps->max_freq)); in rps_boost_show()
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A Dselftest_slpc.c120 *freq = intel_rps_read_actual_frequency(&gt->rps); in measure_power_at_freq()
121 *power = slpc_measure_power(&gt->rps, freq); in measure_power_at_freq()
142 req_freq = intel_rps_read_punit_req_frequency(rps); in vary_max_freq()
151 act_freq = intel_rps_read_actual_frequency(rps); in vary_max_freq()
178 req_freq = intel_rps_read_punit_req_frequency(rps); in vary_min_freq()
187 act_freq = intel_rps_read_actual_frequency(rps); in vary_min_freq()
252 struct intel_gt *gt = rps_to_gt(rps); in max_granted_freq()
281 struct intel_rps *rps = &gt->rps; in run_test() local
363 err = vary_min_freq(slpc, rps, &max_act_freq); in run_test()
367 err = vary_max_freq(slpc, rps, &max_act_freq); in run_test()
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A Dintel_gt_sysfs_pm.c335 return intel_rps_get_rp0_frequency(&gt->rps); in __RP0_freq_mhz_show()
340 return intel_rps_get_rpn_frequency(&gt->rps); in __RPn_freq_mhz_show()
345 return intel_rps_get_rp1_frequency(&gt->rps); in __RP1_freq_mhz_show()
370 struct intel_rps *rps = &gt->rps; in __vlv_rpe_freq_mhz_show() local
372 return intel_gpu_freq(rps, rps->efficient_freq); in __vlv_rpe_freq_mhz_show()
424 #define GEN6_RPS_ATTR GEN6_ATTR(, rps)
725 struct intel_rps *rps = &gt->rps; in rps_up_threshold_pct_show() local
735 struct intel_rps *rps = &gt->rps; in rps_up_threshold_pct_store() local
743 ret = intel_rps_set_up_threshold(rps, val); in rps_up_threshold_pct_store()
759 struct intel_rps *rps = &gt->rps; in rps_down_threshold_pct_show() local
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A Dselftest_llc.c25 struct intel_rps *rps = &llc_to_gt(llc)->rps; in gen6_verify_ring_freq() local
45 intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)), in gen6_verify_ring_freq()
55 intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)), in gen6_verify_ring_freq()
A Dintel_llc.c54 struct intel_rps *rps = &llc_to_gt(llc)->rps; in get_ia_constants() local
66 consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps); in get_ia_constants()
67 consts->max_gpu_freq = intel_rps_get_max_raw_freq(rps); in get_ia_constants()
A Dintel_gt_pm.c94 intel_rps_unpark(&gt->rps); in __gt_unpark()
119 intel_rps_park(&gt->rps); in __gt_park()
158 intel_rps_init(&gt->rps); in intel_gt_pm_init()
214 intel_rps_sanitize(&gt->rps); in gt_sanitize()
279 intel_rps_enable(&gt->rps); in intel_gt_resume()
374 intel_rps_disable(&gt->rps); in intel_gt_suspend_late()
A Dselftest_rc6.c36 struct intel_rps *rps = &gt->rps; in live_rc6_manual() local
81 rc0_freq = intel_rps_read_actual_frequency_fw(rps); in live_rc6_manual()
112 rc6_freq = intel_rps_read_actual_frequency_fw(rps); in live_rc6_manual()
/drivers/gpu/drm/i915/
A Di915_debugfs.c376 struct intel_rps *rps = &to_gt(dev_priv)->rps; in i915_rps_boost_info() local
381 str_yes_no(intel_rps_is_active(rps))); in i915_rps_boost_info()
384 atomic_read(&rps->num_waiters)); in i915_rps_boost_info()
387 intel_gpu_freq(rps, rps->cur_freq), in i915_rps_boost_info()
390 intel_gpu_freq(rps, rps->min_freq), in i915_rps_boost_info()
391 intel_gpu_freq(rps, rps->min_freq_softlimit), in i915_rps_boost_info()
392 intel_gpu_freq(rps, rps->max_freq_softlimit), in i915_rps_boost_info()
393 intel_gpu_freq(rps, rps->max_freq)); in i915_rps_boost_info()
395 intel_gpu_freq(rps, rps->idle_freq), in i915_rps_boost_info()
396 intel_gpu_freq(rps, rps->efficient_freq), in i915_rps_boost_info()
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/drivers/gpu/drm/radeon/
A Drs780_dpm.c37 struct igp_ps *ps = rps->ps_priv; in rs780_get_ps()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
734 if (r600_is_uvd_state(rps->class, rps->class2)) { in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
744 rdev->pm.dpm.uvd_ps = rps; in rs780_parse_pplib_non_clock_info()
748 struct radeon_ps *rps, in rs780_parse_pplib_clock_info() argument
939 struct radeon_ps *rps) in rs780_dpm_print_power_state() argument
943 r600_dpm_print_class_info(rps->class, rps->class2); in rs780_dpm_print_power_state()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
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A Dsumo_dpm.c383 struct radeon_ps *rps) in sumo_program_at() argument
983 struct radeon_ps *rps) in sumo_force_nbp_state() argument
1184 pi->current_rps = *rps; in sumo_update_current_ps()
1195 pi->requested_rps = *rps; in sumo_update_requested_ps()
1415 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1416 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1797 struct radeon_ps *rps) in sumo_dpm_print_power_state() argument
1802 r600_dpm_print_class_info(rps->class, rps->class2); in sumo_dpm_print_power_state()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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A Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
1025 pi->current_rps = *rps; in trinity_update_current_ps()
1031 struct radeon_ps *rps) in trinity_update_requested_ps() argument
1036 pi->requested_rps = *rps; in trinity_update_requested_ps()
1136 struct radeon_ps *rps) in trinity_setup_nbp_sim() argument
1430 if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) { in trinity_adjust_uvd_state()
1647 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1648 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1971 r600_dpm_print_class_info(rps->class, rps->class2); in trinity_dpm_print_power_state()
1973 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
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A Drv770_dpm.c51 struct rv7xx_ps *ps = rps->ps_priv; in rv770_get_ps()
2158 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2159 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2162 if (r600_is_uvd_state(rps->class, rps->class2)) { in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2170 rdev->pm.dpm.boot_ps = rps; in rv7xx_parse_pplib_non_clock_info()
2172 rdev->pm.dpm.uvd_ps = rps; in rv7xx_parse_pplib_non_clock_info()
2435 struct radeon_ps *rps) in rv770_dpm_print_power_state() argument
2440 r600_dpm_print_class_info(rps->class, rps->class2); in rv770_dpm_print_power_state()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
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A Drv6xx_dpm.c38 struct rv6xx_ps *ps = rps->ps_priv; in rv6xx_get_ps()
1795 struct radeon_ps *rps, in rv6xx_parse_pplib_non_clock_info() argument
1802 if (r600_is_uvd_state(rps->class, rps->class2)) { in rv6xx_parse_pplib_non_clock_info()
1806 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
1807 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
1811 rdev->pm.dpm.boot_ps = rps; in rv6xx_parse_pplib_non_clock_info()
1813 rdev->pm.dpm.uvd_ps = rps; in rv6xx_parse_pplib_non_clock_info()
2008 struct radeon_ps *rps) in rv6xx_dpm_print_power_state() argument
2013 r600_dpm_print_class_info(rps->class, rps->class2); in rv6xx_dpm_print_power_state()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
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A Dkv_dpm.c981 struct radeon_ps *rps) in kv_update_current_ps() argument
986 pi->current_rps = *rps; in kv_update_current_ps()
992 struct radeon_ps *rps) in kv_update_requested_ps() argument
997 pi->requested_rps = *rps; in kv_update_requested_ps()
2380 struct radeon_ps *rps, in kv_parse_pplib_non_clock_info() argument
2394 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2395 rps->dclk = 0; in kv_parse_pplib_non_clock_info()
2399 rdev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2403 rdev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2650 r600_dpm_print_class_info(rps->class, rps->class2); in kv_dpm_print_power_state()
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A Dni_dpm.c786 struct radeon_ps *rps) in ni_apply_state_adjust_rules() argument
3562 struct radeon_ps *rps) in ni_update_current_ps() argument
3568 eg_pi->current_rps = *rps; in ni_update_current_ps()
3574 struct radeon_ps *rps) in ni_update_requested_ps() argument
3906 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in ni_parse_pplib_non_clock_info()
3910 rps->vclk = 0; in ni_parse_pplib_non_clock_info()
3911 rps->dclk = 0; in ni_parse_pplib_non_clock_info()
3917 rdev->pm.dpm.uvd_ps = rps; in ni_parse_pplib_non_clock_info()
4289 r600_dpm_print_class_info(rps->class, rps->class2); in ni_dpm_print_power_state()
4291 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
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A Dni_dpm.h233 struct radeon_ps *rps);
235 struct radeon_ps *rps);
247 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
/drivers/comedi/drivers/
A Ds626.c1279 u32 *rps; in s626_reset_adc() local
1345 *rps++ = local_ppl; in s626_reset_adc()
1358 *rps++ = local_ppl; in s626_reset_adc()
1375 (u32)((unsigned long)rps - in s626_reset_adc()
1380 *rps++ = S626_RPS_JUMP; in s626_reset_adc()
1381 *rps++ = jmp_adrs; in s626_reset_adc()
1393 *rps++ = S626_RPS_NOP; in s626_reset_adc()
1407 *rps++ = S626_RPS_STREG | in s626_reset_adc()
1431 *rps++ = S626_RPS_NOP; in s626_reset_adc()
1440 *rps++ = S626_RPS_NOP; in s626_reset_adc()
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/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_fw.c188 before_freq = intel_rps_read_actual_frequency(&gt->rps); in guc_wait_ucode()
196 count, intel_rps_read_actual_frequency(&gt->rps), status, in guc_wait_ucode()
208 status, delta_ms, intel_rps_read_actual_frequency(&gt->rps), ret); in guc_wait_ucode()
263 before_freq, intel_rps_read_actual_frequency(&gt->rps), in guc_wait_ucode()
264 intel_rps_get_requested_frequency(&gt->rps), in guc_wait_ucode()
268 delta_ms, before_freq, intel_rps_read_actual_frequency(&gt->rps), in guc_wait_ucode()
269 intel_rps_get_requested_frequency(&gt->rps), status, count, ret); in guc_wait_ucode()
A Dintel_huc.c469 before_freq = intel_rps_read_actual_frequency(&gt->rps); in intel_huc_wait_for_auth_complete()
481 count, intel_rps_read_actual_frequency(&gt->rps), in intel_huc_wait_for_auth_complete()
492 before_freq, intel_rps_read_actual_frequency(&gt->rps), in intel_huc_wait_for_auth_complete()
493 intel_rps_get_requested_frequency(&gt->rps), in intel_huc_wait_for_auth_complete()
497 delta_ms, before_freq, intel_rps_read_actual_frequency(&gt->rps), in intel_huc_wait_for_auth_complete()
498 intel_rps_get_requested_frequency(&gt->rps), in intel_huc_wait_for_auth_complete()
/drivers/crypto/intel/qat/qat_common/
A Dadf_gen4_hw_data.c345 enum adf_cfg_service_type rps[RP_GROUP_COUNT] = { }; in adf_gen4_get_ring_to_svc_map() enum
357 rps[i] = COMP; in adf_gen4_get_ring_to_svc_map()
373 rps[rp_group] = SYM; in adf_gen4_get_ring_to_svc_map()
376 rps[rp_group] = ASYM; in adf_gen4_get_ring_to_svc_map()
379 rps[rp_group] = COMP; in adf_gen4_get_ring_to_svc_map()
382 rps[rp_group] = 0; in adf_gen4_get_ring_to_svc_map()
388 ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT | in adf_gen4_get_ring_to_svc_map()
389 rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT | in adf_gen4_get_ring_to_svc_map()
390 rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT | in adf_gen4_get_ring_to_svc_map()
391 rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT; in adf_gen4_get_ring_to_svc_map()
/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dkv_dpm.c1213 struct amdgpu_ps *rps) in kv_update_current_ps() argument
1218 pi->current_rps = *rps; in kv_update_current_ps()
1230 pi->requested_rps = *rps; in kv_update_requested_ps()
2659 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2660 rps->dclk = 0; in kv_parse_pplib_non_clock_info()
2668 adev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2889 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2); in kv_dpm_print_power_state()
2892 rps->vclk, rps->dclk); in kv_dpm_print_power_state()
3232 kv_rps = kv_get_ps(rps); in kv_check_state_equal()
3253 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); in kv_check_state_equal()
[all …]
A Dsi_dpm.c3482 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3485 rps->evclk = 0; in si_apply_state_adjust_rules()
3486 rps->ecclk = 0; in si_apply_state_adjust_rules()
3493 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
7185 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in si_parse_pplib_non_clock_info()
7189 rps->vclk = 0; in si_parse_pplib_non_clock_info()
7190 rps->dclk = 0; in si_parse_pplib_non_clock_info()
7562 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_debugfs_print_current_performance_level()
7954 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2); in si_dpm_print_power_state()
8024 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); in si_check_state_equal()
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