Searched refs:saved_reg (Results 1 – 7 of 7) sorted by relevance
| /drivers/irqchip/ |
| A D | irq-imx-irqsteer.c | 38 u32 *saved_reg; member
199 data->saved_reg = devm_kzalloc(&pdev->dev, in imx_irqsteer_probe()
202 if (!data->saved_reg) in imx_irqsteer_probe()
274 data->saved_reg[i] = readl_relaxed(data->regs + in imx_irqsteer_save_regs()
284 writel_relaxed(data->saved_reg[i], in imx_irqsteer_restore_regs()
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| A D | irq-imx-intmux.c | 65 u32 saved_reg; member
316 irqchip_data->saved_reg = readl_relaxed(data->regs + CHANIER(i)); in imx_intmux_runtime_suspend()
338 writel_relaxed(irqchip_data->saved_reg, data->regs + CHANIER(i)); in imx_intmux_runtime_resume()
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| /drivers/tty/serial/ |
| A D | imx.c | 230 unsigned int saved_reg[10]; member
2663 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2664 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2665 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2666 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2667 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2669 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2671 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2672 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2683 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
[all …]
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| /drivers/clk/mvebu/ |
| A D | common.c | 196 u32 saved_reg; member
220 ctrl->saved_reg = readl(ctrl->base); in mvebu_clk_gating_suspend()
226 writel(ctrl->saved_reg, ctrl->base); in mvebu_clk_gating_resume()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| A D | dfp.c | 237 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) { in nv04_dfp_prepare_sel_clk()
238 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1; in nv04_dfp_prepare_sel_clk()
289 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()
606 (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals); in nv04_dfp_restore()
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| A D | crtc.c | 467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
546 …regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TV… in nv_crtc_mode_set_regs()
677 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; in nv_crtc_save()
697 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; in nv_crtc_restore()
702 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); in nv_crtc_restore()
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| A D | disp.h | 85 struct nv04_mode_state saved_reg; member
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