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Searched refs:scl_data (Results 1 – 25 of 39) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_dscl.c307 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp401_dscl_set_scl_filter()
309 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp401_dscl_set_scl_filter()
312 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); in dpp401_dscl_set_scl_filter()
314 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); in dpp401_dscl_set_scl_filter()
320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp401_dscl_set_scl_filter()
323 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp401_dscl_set_scl_filter()
1082 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) in dpp401_dscl_set_scaler_manual_scale()
1093 dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level; in dpp401_dscl_set_scaler_manual_scale()
1094 memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta, in dpp401_dscl_set_scaler_manual_scale()
1097 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) in dpp401_dscl_set_scaler_manual_scale()
[all …]
A Ddcn401_dpp.c293 scl_data->viewport.width : scl_data->recout.width; in dscl401_calc_lb_num_partitions()
295 scl_data->viewport_c.width : scl_data->recout.width; in dscl401_calc_lb_num_partitions()
316 if (scl_data->viewport.width == scl_data->h_active && in dscl401_calc_lb_num_partitions()
317 scl_data->viewport.height == scl_data->v_active) { in dscl401_calc_lb_num_partitions()
330 if (scl_data->viewport.width == scl_data->h_active && in dscl401_calc_lb_num_partitions()
331 scl_data->viewport.height == scl_data->v_active) { in dscl401_calc_lb_num_partitions()
368 scl_data->viewport.width : scl_data->recout.width; in dscl401_spl_calc_lb_num_partitions()
370 scl_data->viewport_c.width : scl_data->recout.width; in dscl401_spl_calc_lb_num_partitions()
391 if (scl_data->viewport.width == scl_data->h_active && in dscl401_spl_calc_lb_num_partitions()
392 scl_data->viewport.height == scl_data->v_active) { in dscl401_spl_calc_lb_num_partitions()
[all …]
/drivers/gpu/drm/amd/display/dc/sspl/
A Ddc_spl.c462 spl_scratch->scl_data.ratios.horz_c = spl_scratch->scl_data.ratios.horz; in spl_calculate_scaling_ratios()
463 spl_scratch->scl_data.ratios.vert_c = spl_scratch->scl_data.ratios.vert; in spl_calculate_scaling_ratios()
506 spl_swap(spl_scratch->scl_data.viewport.width, spl_scratch->scl_data.viewport.height); in spl_calculate_viewport_size()
507 spl_swap(spl_scratch->scl_data.viewport_c.width, spl_scratch->scl_data.viewport_c.height); in spl_calculate_viewport_size()
715 spl_swap(spl_scratch->scl_data.viewport.x, spl_scratch->scl_data.viewport.y); in spl_calculate_inits_and_viewports()
716 spl_swap(spl_scratch->scl_data.viewport.width, spl_scratch->scl_data.viewport.height); in spl_calculate_inits_and_viewports()
717 spl_swap(spl_scratch->scl_data.viewport_c.x, spl_scratch->scl_data.viewport_c.y); in spl_calculate_inits_and_viewports()
718 spl_swap(spl_scratch->scl_data.viewport_c.width, spl_scratch->scl_data.viewport_c.height); in spl_calculate_inits_and_viewports()
979 if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && in spl_get_optimal_number_of_taps()
1206 bot = spl_fixpt_add(scl_data->inits.v, scl_data->ratios.vert); in spl_set_manual_ratio_init_data()
[all …]
A Ddc_spl_types.h416 struct spl_scaler_data scl_data; member
524 const struct spl_scaler_data *scl_data,
/drivers/gpu/drm/amd/display/dc/dpp/dcn32/
A Ddcn32_dpp.c44 scl_data->viewport.width : scl_data->recout.width; in dscl32_calc_lb_num_partitions()
46 scl_data->viewport_c.width : scl_data->recout.width; in dscl32_calc_lb_num_partitions()
67 if (scl_data->viewport.width == scl_data->h_active && in dscl32_calc_lb_num_partitions()
68 scl_data->viewport.height == scl_data->v_active) { in dscl32_calc_lb_num_partitions()
81 if (scl_data->viewport.width == scl_data->h_active && in dscl32_calc_lb_num_partitions()
82 scl_data->viewport.height == scl_data->v_active) { in dscl32_calc_lb_num_partitions()
177 scl_data->viewport.width : scl_data->recout.width; in dscl32_spl_calc_lb_num_partitions()
179 scl_data->viewport_c.width : scl_data->recout.width; in dscl32_spl_calc_lb_num_partitions()
200 if (scl_data->viewport.width == scl_data->h_active && in dscl32_spl_calc_lb_num_partitions()
201 scl_data->viewport.height == scl_data->v_active) { in dscl32_spl_calc_lb_num_partitions()
[all …]
A Ddcn32_dpp.h40 const struct spl_scaler_data *scl_data,
/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
A Ddcn201_dpp.c192 struct scaler_data *scl_data, in dpp201_get_optimal_number_of_taps() argument
196 if (scl_data->viewport.width != scl_data->h_active && in dpp201_get_optimal_number_of_taps()
197 scl_data->viewport.height != scl_data->v_active && in dpp201_get_optimal_number_of_taps()
202 if (scl_data->viewport.width > scl_data->h_active && in dpp201_get_optimal_number_of_taps()
220 scl_data->taps.h_taps = 8; in dpp201_get_optimal_number_of_taps()
222 scl_data->taps.h_taps = 4; in dpp201_get_optimal_number_of_taps()
228 scl_data->taps.v_taps = 8; in dpp201_get_optimal_number_of_taps()
230 scl_data->taps.v_taps = 4; in dpp201_get_optimal_number_of_taps()
235 scl_data->taps.v_taps_c = 4; in dpp201_get_optimal_number_of_taps()
253 scl_data->taps.h_taps = 1; in dpp201_get_optimal_number_of_taps()
[all …]
A Ddcn201_dpp.h72 struct scaler_data scl_data; member
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_dscl.c297 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
300 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter()
317 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
319 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
326 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); in dpp1_dscl_set_scl_filter()
328 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); in dpp1_dscl_set_scl_filter()
400 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dpp1_dscl_calc_lb_num_partitions()
401 scl_data->viewport.width : scl_data->recout.width; in dpp1_dscl_calc_lb_num_partitions()
403 scl_data->viewport_c.width : scl_data->recout.width; in dpp1_dscl_calc_lb_num_partitions()
623 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) in dpp1_dscl_set_scaler_manual_scale()
[all …]
A Ddcn10_dpp.c126 struct scaler_data *scl_data, in dpp1_get_optimal_number_of_taps() argument
136 if (scl_data->viewport.width > scl_data->h_active && in dpp1_get_optimal_number_of_taps()
155 scl_data->taps.h_taps = 4; in dpp1_get_optimal_number_of_taps()
159 scl_data->taps.v_taps = 4; in dpp1_get_optimal_number_of_taps()
163 scl_data->taps.v_taps_c = 2; in dpp1_get_optimal_number_of_taps()
167 scl_data->taps.h_taps_c = 2; in dpp1_get_optimal_number_of_taps()
176 scl_data->taps.h_taps = 1; in dpp1_get_optimal_number_of_taps()
178 scl_data->taps.v_taps = 1; in dpp1_get_optimal_number_of_taps()
180 scl_data->taps.h_taps_c = 1; in dpp1_get_optimal_number_of_taps()
182 scl_data->taps.v_taps_c = 1; in dpp1_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
A Ddcn20_dpp.c261 const struct scaler_data *scl_data, in dscl2_calc_lb_num_partitions() argument
269 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions()
270 scl_data->viewport.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions()
271 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions()
272 scl_data->viewport_c.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions()
306 if (scl_data->lb_params.alpha_en in dscl2_calc_lb_num_partitions()
438 const struct spl_scaler_data *scl_data, in dscl2_spl_calc_lb_num_partitions() argument
446 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl2_spl_calc_lb_num_partitions()
447 scl_data->viewport.width : scl_data->recout.width; in dscl2_spl_calc_lb_num_partitions()
448 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl2_spl_calc_lb_num_partitions()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp.c420 struct scaler_data *scl_data, in dpp3_get_optimal_number_of_taps() argument
435 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
437 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
442 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
444 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps()
451 scl_data->taps.v_taps_c = 4; in dpp3_get_optimal_number_of_taps()
456 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8); in dpp3_get_optimal_number_of_taps()
458 scl_data->taps.h_taps_c = 4; in dpp3_get_optimal_number_of_taps()
466 if (scl_data->viewport.width > scl_data->h_active && in dpp3_get_optimal_number_of_taps()
508 scl_data->taps.h_taps = 1; in dpp3_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dce60/
A Ddce60_hwseq.c202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color()
248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
371 pipe_ctx->plane_res.scl_data.viewport.width, in dce60_program_front_end_for_pipe()
372 pipe_ctx->plane_res.scl_data.viewport.height, in dce60_program_front_end_for_pipe()
373 pipe_ctx->plane_res.scl_data.viewport.x, in dce60_program_front_end_for_pipe()
374 pipe_ctx->plane_res.scl_data.viewport.y, in dce60_program_front_end_for_pipe()
375 pipe_ctx->plane_res.scl_data.recout.width, in dce60_program_front_end_for_pipe()
376 pipe_ctx->plane_res.scl_data.recout.height, in dce60_program_front_end_for_pipe()
377 pipe_ctx->plane_res.scl_data.recout.x, in dce60_program_front_end_for_pipe()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
412 switch (pipe->plane_res.scl_data.lb_params.depth) { in pipe_ctx_to_e2e_pipe_params()
949 + pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
951 + pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
955 - pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
958 - pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
961 + pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
963 + pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
967 - pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
970 - pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/
A Ddc_spl_translate.c98 populate_splformat_from_format(&spl_in->basic_in.format, pipe_ctx->plane_res.scl_data.format); in translate_SPL_in_params_from_pipe_ctx()
139 spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en; in translate_SPL_in_params_from_pipe_ctx()
197 spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; in translate_SPL_in_params_from_pipe_ctx()
198 spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; in translate_SPL_in_params_from_pipe_ctx()
218 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout); in translate_SPL_out_params_to_pipe_ctx()
220 …populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->rat… in translate_SPL_out_params_to_pipe_ctx()
222 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewp… in translate_SPL_out_params_to_pipe_ctx()
224 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->vie… in translate_SPL_out_params_to_pipe_ctx()
226 populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps); in translate_SPL_out_params_to_pipe_ctx()
228 populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init); in translate_SPL_out_params_to_pipe_ctx()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.c1165 struct scaler_data *scl_data, in dce_transform_get_optimal_number_of_taps() argument
1173 (scl_data->viewport.width > scl_data->recout.width)) in dce_transform_get_optimal_number_of_taps()
1178 scl_data->lb_params.depth, in dce_transform_get_optimal_number_of_taps()
1194 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); in dce_transform_get_optimal_number_of_taps()
1195 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); in dce_transform_get_optimal_number_of_taps()
1196 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); in dce_transform_get_optimal_number_of_taps()
1197 scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true); in dce_transform_get_optimal_number_of_taps()
1203 && scl_data->taps.v_taps > 1) { in dce_transform_get_optimal_number_of_taps()
1207 if (scl_data->taps.v_taps <= 1) in dce_transform_get_optimal_number_of_taps()
1213 if (max_num_of_lines <= scl_data->taps.v_taps_c && scl_data->taps.v_taps_c > 1) { in dce_transform_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_resource.c1123 &pipe_ctx->plane_res.scl_data.recout, in calculate_recout()
1165 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; in calculate_scaling_ratios()
1166 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios()
1560 &pipe_ctx->plane_res.scl_data, in resource_build_scaling_params()
1566 &pipe_ctx->plane_res.scl_data, in resource_build_scaling_params()
1590 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; in resource_build_scaling_params()
1592 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; in resource_build_scaling_params()
1613 pipe_ctx->plane_res.scl_data.recout.x, in resource_build_scaling_params()
1614 pipe_ctx->plane_res.scl_data.recout.y, in resource_build_scaling_params()
1615 pipe_ctx->plane_res.scl_data.h_active, in resource_build_scaling_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_transform_v.c48 const struct scaler_data *scl_data, in calculate_viewport() argument
53 luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; in calculate_viewport()
54 luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; in calculate_viewport()
56 scl_data->viewport.width - scl_data->viewport.width % 2; in calculate_viewport()
58 scl_data->viewport.height - scl_data->viewport.height % 2; in calculate_viewport()
64 if (scl_data->format == PIXEL_FORMAT_420BPP8) { in calculate_viewport()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dtransform.h173 const struct scaler_data *scl_data);
182 struct scaler_data *scl_data,
286 const struct scaler_data *scl_data,
A Ddpp.h231 const struct scaler_data *scl_data);
240 struct scaler_data *scl_data,
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_trace.h439 __entry->recout_x = plane_res->scl_data.recout.x;
440 __entry->recout_y = plane_res->scl_data.recout.y;
441 __entry->recout_w = plane_res->scl_data.recout.width;
442 __entry->recout_h = plane_res->scl_data.recout.height;
443 __entry->viewport_x = plane_res->scl_data.viewport.x;
444 __entry->viewport_y = plane_res->scl_data.viewport.y;
445 __entry->viewport_w = plane_res->scl_data.viewport.width;
446 __entry->viewport_h = plane_res->scl_data.viewport.height;
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c3053 &pipe_ctx->plane_res.scl_data.viewport, in dcn10_update_dchubp_dpp()
3054 &pipe_ctx->plane_res.scl_data.viewport_c); in dcn10_update_dchubp_dpp()
3616 .viewport = pipe_ctx->plane_res.scl_data.viewport, in dcn10_set_cursor_position()
3713 pipe_ctx->plane_res.scl_data.viewport.width; in dcn10_set_cursor_position()
3715 pipe_ctx->plane_res.scl_data.viewport.x; in dcn10_set_cursor_position()
3743 (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x; in dcn10_set_cursor_position()
3750 pipe_ctx->plane_res.scl_data.viewport.height; in dcn10_set_cursor_position()
3752 pipe_ctx->plane_res.scl_data.viewport.y; in dcn10_set_cursor_position()
3777 pipe_ctx->top_pipe->plane_res.scl_data.viewport.y; in dcn10_set_cursor_position()
3806 pipe_ctx->plane_res.scl_data.viewport.width; in dcn10_set_cursor_position()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c1497 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1515 &pipe_ctx->plane_res.scl_data); in program_scaler()
3009 pipe_ctx->plane_res.scl_data.viewport.width, in dce110_program_front_end_for_pipe()
3010 pipe_ctx->plane_res.scl_data.viewport.height, in dce110_program_front_end_for_pipe()
3011 pipe_ctx->plane_res.scl_data.viewport.x, in dce110_program_front_end_for_pipe()
3012 pipe_ctx->plane_res.scl_data.viewport.y, in dce110_program_front_end_for_pipe()
3013 pipe_ctx->plane_res.scl_data.recout.width, in dce110_program_front_end_for_pipe()
3014 pipe_ctx->plane_res.scl_data.recout.height, in dce110_program_front_end_for_pipe()
3015 pipe_ctx->plane_res.scl_data.recout.x, in dce110_program_front_end_for_pipe()
3016 pipe_ctx->plane_res.scl_data.recout.y); in dce110_program_front_end_for_pipe()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c830 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane()
839 return &temp_pipe->plane_res.scl_data; in get_scaler_data_for_plane()
1232 mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x; in dml21_get_pipe_mcache_config()
1233 mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width; in dml21_get_pipe_mcache_config()
1235 mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x; in dml21_get_pipe_mcache_config()
1236 mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width; in dml21_get_pipe_mcache_config()
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c1067 .viewport = pipe_ctx->plane_res.scl_data.viewport, in dcn401_set_cursor_position()
1068 .recout = pipe_ctx->plane_res.scl_data.recout, in dcn401_set_cursor_position()
1069 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dcn401_set_cursor_position()
1070 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn401_set_cursor_position()
1090 (pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) { in dcn401_set_cursor_position()
1174 bottom_pipe_x_pos = x_pos - pipe_ctx->plane_res.scl_data.recout.x; in dcn401_set_cursor_position()
1176 x_pos = pipe_ctx->plane_res.scl_data.recout.x; in dcn401_set_cursor_position()
2555 …if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data… in dcn401_detect_pipe_changes()
2558 …if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(… in dcn401_detect_pipe_changes()
2559 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, in dcn401_detect_pipe_changes()
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