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Searched refs:sclk_dpm_enable_mask (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/radeon/
A Dci_dpm.h110 u32 sclk_dpm_enable_mask; member
A Dci_dpm.c3261 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3771 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3774 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
4126 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4182 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4184 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4221 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4223 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu7_hwmgr.h167 uint32_t sclk_dpm_enable_mask; member
A Dvega10_hwmgr.h177 uint32_t sclk_dpm_enable_mask; member
A Dvega12_hwmgr.h154 uint32_t sclk_dpm_enable_mask; member
A Dsmu7_hwmgr.c3050 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_highest()
3052 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_force_dpm_highest()
3091 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()
3094 data->dpm_level_enable_mask.sclk_dpm_enable_mask, in smu7_upload_dpm_level_enable_mask()
3132 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_lowest()
3134 data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_force_dpm_lowest()
4357 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in smu7_generate_dpm_level_enable_mask()
4931 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask, in smu7_force_clock_level()
5626 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_patch_compute_profile_mode()
5628 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_patch_compute_profile_mode()
[all …]
A Dvega20_hwmgr.h208 uint32_t sclk_dpm_enable_mask; member
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dvegam_smumgr.c910 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in vegam_populate_all_graphic_levels()
915 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_graphic_levels()
A Dpolaris10_smumgr.c1099 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in polaris10_populate_all_graphic_levels()
1104 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i; in polaris10_populate_all_graphic_levels()
A Dfiji_smumgr.c1043 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in fiji_populate_all_graphic_levels()
A Diceland_smumgr.c1002 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in iceland_populate_all_graphic_levels()
A Dci_smumgr.c502 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
A Dtonga_smumgr.c732 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in tonga_populate_all_graphic_levels()

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