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Searched refs:sdma_rlc_reg_offset (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_amdkfd_arcturus.c72 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
114 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
118 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
120 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
127 uint32_t sdma_rlc_reg_offset; in kgd_arcturus_hqd_sdma_load() local
207 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_arcturus_hqd_sdma_dump()
209 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_arcturus_hqd_sdma_dump()
212 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_arcturus_hqd_sdma_dump()
215 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_arcturus_hqd_sdma_dump()
227 uint32_t sdma_rlc_reg_offset; in kgd_arcturus_hqd_sdma_is_occupied() local
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A Damdgpu_amdkfd_gfx_v10_3.c134 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
160 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
164 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
166 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
363 uint32_t sdma_rlc_reg_offset; in hqd_sdma_load_v10_3() local
443 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v10_3()
445 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v10_3()
448 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v10_3()
451 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v10_3()
485 uint32_t sdma_rlc_reg_offset; in hqd_sdma_is_occupied_v10_3() local
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A Damdgpu_amdkfd_gc_9_4_3.c63 uint32_t sdma_rlc_reg_offset; in kgd_gfx_v9_4_3_hqd_sdma_load() local
73 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL, in kgd_gfx_v9_4_3_hqd_sdma_load()
94 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR, in kgd_gfx_v9_4_3_hqd_sdma_load()
101 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR, in kgd_gfx_v9_4_3_hqd_sdma_load()
106 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR, in kgd_gfx_v9_4_3_hqd_sdma_load()
149 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_gfx_v9_4_3_hqd_sdma_dump()
151 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_gfx_v9_4_3_hqd_sdma_dump()
154 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_gfx_v9_4_3_hqd_sdma_dump()
157 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_gfx_v9_4_3_hqd_sdma_dump()
168 uint32_t sdma_rlc_reg_offset; in kgd_gfx_v9_4_3_hqd_sdma_is_occupied() local
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A Damdgpu_amdkfd_gfx_v11.c130 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
149 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
151 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
348 uint32_t sdma_rlc_reg_offset; in hqd_sdma_load_v11() local
429 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()
432 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()
435 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()
438 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()
441 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()
473 uint32_t sdma_rlc_reg_offset; in hqd_sdma_is_occupied_v11() local
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A Damdgpu_amdkfd_gfx_v7.c244 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
248 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_load()
250 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
268 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
274 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
280 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, in kgd_hqd_sdma_load()
345 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_is_occupied() local
349 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_is_occupied()
464 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_destroy() local
469 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_destroy()
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A Damdgpu_amdkfd_gfx_v8.c268 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
272 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_load()
273 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
291 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
297 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
303 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, in kgd_hqd_sdma_load()
377 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_is_occupied() local
381 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_is_occupied()
499 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_destroy() local
504 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_destroy()
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A Damdgpu_amdkfd_gfx_v10.c377 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
387 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
408 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
415 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
457 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
459 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
462 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
465 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
498 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_is_occupied() local
630 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_destroy() local
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A Damdgpu_amdkfd_gfx_v9.c185 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
203 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
207 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
209 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
388 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
468 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
470 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
473 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
476 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
509 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_is_occupied() local
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A Damdgpu_amdkfd_gfx_v12.c81 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
96 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
100 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
102 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
140 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, in hqd_sdma_dump_v12() local
155 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v12()

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