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Searched refs:sel (Results 1 – 25 of 293) sorted by relevance

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/drivers/staging/media/starfive/camss/
A Dstf-isp.c162 sel.which = fmt->which; in isp_set_format()
205 switch (sel->target) { in isp_get_selection()
209 sel->pad); in isp_get_selection()
210 sel->r.left = 0; in isp_get_selection()
211 sel->r.top = 0; in isp_get_selection()
216 sel->r = *rect; in isp_get_selection()
225 sel->r = *rect; in isp_get_selection()
254 *rect = sel->r; in isp_set_selection()
271 *rect = sel->r; in isp_set_selection()
274 fmt.which = sel->which; in isp_set_selection()
[all …]
/drivers/media/platform/renesas/vsp1/
A Dvsp1_histo.c220 sel->r.left = 0; in histo_get_selection()
221 sel->r.top = 0; in histo_get_selection()
229 sel->r.left = 0; in histo_get_selection()
230 sel->r.top = 0; in histo_get_selection()
236 sel->r = *v4l2_subdev_state_get_compose(state, sel->pad); in histo_get_selection()
240 sel->r = *v4l2_subdev_state_get_crop(state, sel->pad); in histo_get_selection()
269 *v4l2_subdev_state_get_crop(sd_state, sel->pad) = sel->r; in histo_set_crop()
270 *v4l2_subdev_state_get_compose(sd_state, sel->pad) = sel->r; in histo_set_crop()
288 sel->r.left = 0; in histo_set_compose()
289 sel->r.top = 0; in histo_set_compose()
[all …]
A Dvsp1_rwpf.c199 sel->r.left = 0; in vsp1_rwpf_get_selection()
200 sel->r.top = 0; in vsp1_rwpf_get_selection()
251 sel->r.left = ALIGN(sel->r.left, 2); in vsp1_rwpf_set_selection()
252 sel->r.top = ALIGN(sel->r.top, 2); in vsp1_rwpf_set_selection()
253 sel->r.width = round_down(sel->r.width, 2); in vsp1_rwpf_set_selection()
254 sel->r.height = round_down(sel->r.height, 2); in vsp1_rwpf_set_selection()
257 sel->r.left = min_t(unsigned int, sel->r.left, format->width - 2); in vsp1_rwpf_set_selection()
258 sel->r.top = min_t(unsigned int, sel->r.top, format->height - 2); in vsp1_rwpf_set_selection()
259 sel->r.width = min_t(unsigned int, sel->r.width, in vsp1_rwpf_set_selection()
261 sel->r.height = min_t(unsigned int, sel->r.height, in vsp1_rwpf_set_selection()
[all …]
A Dvsp1_uif.c93 if (sel->pad != UIF_PAD_SINK) in uif_get_selection()
104 switch (sel->target) { in uif_get_selection()
108 sel->r.left = 0; in uif_get_selection()
109 sel->r.top = 0; in uif_get_selection()
110 sel->r.width = format->width; in uif_get_selection()
115 sel->r = *v4l2_subdev_state_get_crop(state, sel->pad); in uif_get_selection()
153 sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1); in uif_set_selection()
154 sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1); in uif_set_selection()
155 sel->r.width = clamp_t(unsigned int, sel->r.width, UIF_MIN_SIZE, in uif_set_selection()
157 sel->r.height = clamp_t(unsigned int, sel->r.height, UIF_MIN_SIZE, in uif_set_selection()
[all …]
A Dvsp1_brx.c192 switch (sel->target) { in brx_get_selection()
194 sel->r.left = 0; in brx_get_selection()
195 sel->r.top = 0; in brx_get_selection()
196 sel->r.width = BRX_MAX_SIZE; in brx_get_selection()
197 sel->r.height = BRX_MAX_SIZE; in brx_get_selection()
202 sel->which); in brx_get_selection()
207 sel->r = *v4l2_subdev_state_get_compose(state, sel->pad); in brx_get_selection()
245 sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1); in brx_set_selection()
246 sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1); in brx_set_selection()
253 sel->r.width = format->width; in brx_set_selection()
[all …]
/drivers/power/supply/
A Dmt6360_charger.c262 sel = (sel & MT6360_ICHG_MASK) >> MT6360_ICHG_SHFT; in mt6360_charger_get_ichg()
285 sel = (sel & MT6360_VOREG_MASK) >> MT6360_VOREG_SHFT; in mt6360_charger_get_cv()
308 sel = (sel & MT6360_IAICR_MASK) >> MT6360_IAICR_SHFT; in mt6360_charger_get_aicr()
356 sel = (sel & MT6360_IEOC_MASK) >> MT6360_IEOC_SHFT; in mt6360_charger_get_ieoc()
377 u32 sel; in mt6360_charger_set_ichg() local
389 u32 sel; in mt6360_charger_set_cv() local
401 u32 sel; in mt6360_charger_set_aicr() local
413 u32 sel; in mt6360_charger_set_mivr() local
425 u32 sel; in mt6360_charger_set_iprechg() local
437 u32 sel; in mt6360_charger_set_ieoc() local
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/drivers/net/ethernet/broadcom/asp2/
A Dbcmasp.h74 #define ASP_RX_FILTER_MDA_CFG(sel) (((sel) * 0x14) + 0x100) argument
78 #define ASP_RX_FILTER_MDA_PAT_H(sel) (((sel) * 0x14) + 0x104) argument
79 #define ASP_RX_FILTER_MDA_PAT_L(sel) (((sel) * 0x14) + 0x108) argument
80 #define ASP_RX_FILTER_MDA_MSK_H(sel) (((sel) * 0x14) + 0x10c) argument
81 #define ASP_RX_FILTER_MDA_MSK_L(sel) (((sel) * 0x14) + 0x110) argument
82 #define ASP_RX_FILTER_MDA_CFG(sel) (((sel) * 0x14) + 0x100) argument
87 #define ASP_RX_FILTER_NET_CFG(sel) (((sel) * 0xa04) + 0x400) argument
88 #define ASP_RX_FILTER_NET_CFG_CH(sel) ((sel) << 0) argument
93 #define ASP_RX_FILTER_NET_CFG_L3_FRM(sel) ((sel) << 13) argument
94 #define ASP_RX_FILTER_NET_CFG_L4_FRM(sel) ((sel) << 15) argument
[all …]
/drivers/regulator/
A Danatop-regulator.c31 int sel; member
63 int sel; in anatop_regmap_enable() local
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
101 return anatop_reg->sel; in anatop_regmap_core_get_voltage_sel()
109 int sel; in anatop_regmap_get_bypass() local
112 if (sel == LDO_FET_FULL_ON) in anatop_regmap_get_bypass()
124 int sel; in anatop_regmap_set_bypass() local
129 sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_set_bypass()
269 sreg->sel = 0; in anatop_regulator_probe()
279 sreg->sel = 22; in anatop_regulator_probe()
[all …]
A Dhelpers.c216 sel -= voltages_in_range; in regulator_set_voltage_sel_pickable_regmap()
432 unsigned int sel; in regulator_map_voltage_linear_range() local
448 ret = sel; in regulator_map_voltage_linear_range()
492 unsigned int sel; in regulator_map_voltage_pickable_linear_range() local
821 int i, sel = -1; in regulator_set_current_limit_regmap() local
835 sel = i; in regulator_set_current_limit_regmap()
843 sel = i; in regulator_set_current_limit_regmap()
850 if (sel < 0) in regulator_set_current_limit_regmap()
954 *sel = s; in regulator_find_closest_bigger()
963 *sel = maxsel; in regulator_find_closest_bigger()
[all …]
A Dmax77693-regulator.c60 unsigned int reg, sel; in max77693_chg_get_current_limit() local
68 sel = reg & reg_data->linear_mask; in max77693_chg_get_current_limit()
71 if (sel <= reg_data->min_sel) in max77693_chg_get_current_limit()
72 sel = 0; in max77693_chg_get_current_limit()
74 sel -= reg_data->min_sel; in max77693_chg_get_current_limit()
76 val = chg_min_uA + reg_data->uA_step * sel; in max77693_chg_get_current_limit()
88 int sel = 0; in max77693_chg_set_current_limit() local
90 while (chg_min_uA + reg_data->uA_step * sel < min_uA) in max77693_chg_set_current_limit()
91 sel++; in max77693_chg_set_current_limit()
93 if (chg_min_uA + reg_data->uA_step * sel > max_uA) in max77693_chg_set_current_limit()
[all …]
/drivers/clk/bcm/
A Dclk-kona-setup.c13 #define selector_clear_exists(sel) ((sel)->width = 0) argument
46 struct bcm_clk_sel *sel; in clk_requires_trigger() local
52 sel = &peri->sel; in clk_requires_trigger()
53 if (sel->parent_count && selector_exists(sel)) in clk_requires_trigger()
76 struct bcm_clk_sel *sel; in peri_clk_data_offsets_valid() local
140 sel = &peri->sel; in peri_clk_data_offsets_valid()
286 if (!bitfield_valid(sel->shift, sel->width, field_name, clock_name)) in sel_valid()
301 max_sel = sel->parent_sel[sel->parent_count - 1]; in sel_valid()
307 sel->width); in sel_valid()
429 sel = &peri->sel; in peri_clk_data_valid()
[all …]
A Dclk-bcm281xx.c38 .sel = SELECTOR(0x0a10, 0, 2),
47 .sel = SELECTOR(0x0a04, 0, 2),
55 .sel = SELECTOR(0x0a00, 0, 2),
79 .sel = SELECTOR(0x0e74, 0, 2),
101 .sel = SELECTOR(0x0a28, 0, 3),
113 .sel = SELECTOR(0x0a2c, 0, 3),
125 .sel = SELECTOR(0x0a34, 0, 3),
137 .sel = SELECTOR(0x0a30, 0, 3),
148 .sel = SELECTOR(0x0a24, 0, 2),
158 .sel = SELECTOR(0x0a38, 0, 2),
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A Dclk-kona.c823 if (!selector_exists(sel)) in selector_read_index()
831 parent_sel = bitfield_extract(reg_val, sel->shift, sel->width); in selector_read_index()
868 parent_sel = bitfield_extract(reg_val, sel->shift, sel->width); in __sel_commit()
872 sel->clk_index = index; in __sel_commit()
877 BUG_ON((u32)sel->clk_index >= sel->parent_count); in __sel_commit()
878 parent_sel = sel->parent_sel[sel->clk_index]; in __sel_commit()
887 reg_val = bitfield_replace(reg_val, sel->shift, sel->width, parent_sel); in __sel_commit()
909 if (!selector_exists(sel)) in sel_init()
927 previous = sel->clk_index; in selector_write()
931 sel->clk_index = index; in selector_write()
[all …]
A Dclk-bcm21664.c38 .sel = SELECTOR(0x0a10, 0, 2),
64 .sel = SELECTOR(0x0a28, 0, 3),
76 .sel = SELECTOR(0x0a2c, 0, 3),
88 .sel = SELECTOR(0x0a34, 0, 3),
100 .sel = SELECTOR(0x0a30, 0, 3),
159 .sel = SELECTOR(0x0a10, 0, 2),
169 .sel = SELECTOR(0x0a14, 0, 2),
179 .sel = SELECTOR(0x0a18, 0, 2),
191 .sel = SELECTOR(0x0a64, 0, 3),
202 .sel = SELECTOR(0x0a68, 0, 3),
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/drivers/media/platform/nxp/imx8-isi/
A Dimx8-isi-pipe.c563 sel->r.top = 0; in mxc_isi_pipe_get_selection()
576 sel->r = *rect; in mxc_isi_pipe_get_selection()
585 sel->r = *rect; in mxc_isi_pipe_get_selection()
594 sel->r = *rect; in mxc_isi_pipe_get_selection()
621 sel->r.left = clamp_t(s32, sel->r.left, 0, rect->width - 1); in mxc_isi_pipe_set_selection()
622 sel->r.top = clamp_t(s32, sel->r.top, 0, rect->height - 1); in mxc_isi_pipe_set_selection()
623 sel->r.width = clamp(sel->r.width, MXC_ISI_MIN_WIDTH, in mxc_isi_pipe_set_selection()
625 sel->r.height = clamp(sel->r.height, MXC_ISI_MIN_HEIGHT, in mxc_isi_pipe_set_selection()
650 sel->r.width = clamp(sel->r.width, MXC_ISI_MIN_WIDTH, in mxc_isi_pipe_set_selection()
652 sel->r.height = clamp(sel->r.height, MXC_ISI_MIN_HEIGHT, in mxc_isi_pipe_set_selection()
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/drivers/media/platform/amlogic/c3/isp/
A Dc3-isp-resizer.c652 sel->r.top = 0; in c3_isp_rsz_get_selection()
659 sel->r.top = 0; in c3_isp_rsz_get_selection()
663 sel->r = *crop; in c3_isp_rsz_get_selection()
667 sel->r = *cmps; in c3_isp_rsz_get_selection()
696 sel->r.left = clamp_t(s32, sel->r.left, 0, fmt->width - 1); in c3_isp_rsz_set_selection()
697 sel->r.top = clamp_t(s32, sel->r.top, 0, fmt->height - 1); in c3_isp_rsz_set_selection()
698 sel->r.width = clamp(sel->r.width, C3_ISP_MIN_WIDTH, in c3_isp_rsz_set_selection()
700 sel->r.height = clamp(sel->r.height, C3_ISP_MIN_HEIGHT, in c3_isp_rsz_set_selection()
714 sel->r = *crop; in c3_isp_rsz_set_selection()
722 sel->r.width = clamp(sel->r.width, C3_ISP_MIN_WIDTH, in c3_isp_rsz_set_selection()
[all …]
/drivers/firmware/
A Ddmi-sysfs.c273 struct dmi_system_event_log sel; \
276 memcpy(&sel, dh, sizeof(sel)); \
326 ret = inb(sel->io.data_addr); in read_sel_8bit_indexed_io()
339 ret = inb(sel->io.data_addr); in read_sel_2x8bit_indexed_io()
351 ret = inb(sel->io.data_addr); in read_sel_16bit_indexed_io()
372 *(buf++) = io_reader(sel, pos++); in dmi_sel_raw_read_io()
387 mapped = dmi_remap(sel->access_method_address, sel->area_length); in dmi_sel_raw_read_phys32()
406 struct dmi_system_event_log sel; in dmi_sel_raw_read_helper() local
411 memcpy(&sel, dh, sizeof(sel)); in dmi_sel_raw_read_helper()
413 switch (sel.access_method) { in dmi_sel_raw_read_helper()
[all …]
/drivers/media/pci/intel/ipu6/
A Dipu6-isys-csi2.c411 if (sel->pad == CSI2_PAD_SINK || sel->target != V4L2_SEL_TGT_CROP) in ipu6_isys_csi2_set_sel()
415 sel->pad, in ipu6_isys_csi2_set_sel()
424 crop = v4l2_subdev_state_get_crop(state, sel->pad, sel->stream); in ipu6_isys_csi2_set_sel()
429 sel->r.left = 0; in ipu6_isys_csi2_set_sel()
434 sel->r.height = clamp(sel->r.height & ~1, IPU6_ISYS_MIN_HEIGHT, in ipu6_isys_csi2_set_sel()
436 *crop = sel->r; in ipu6_isys_csi2_set_sel()
446 sd->name, sel->r.left, sel->r.top, sel->r.width, sel->r.height, in ipu6_isys_csi2_set_sel()
464 sel->pad, in ipu6_isys_csi2_get_sel()
469 crop = v4l2_subdev_state_get_crop(state, sel->pad, sel->stream); in ipu6_isys_csi2_get_sel()
477 sel->r.top = 0; in ipu6_isys_csi2_get_sel()
[all …]
/drivers/staging/media/ipu7/
A Dipu7-isys-csi2.c206 sel->pad, in ipu7_isys_csi2_set_sel()
215 crop = v4l2_subdev_state_get_crop(state, sel->pad, sel->stream); in ipu7_isys_csi2_set_sel()
220 sel->r.left = 0; in ipu7_isys_csi2_set_sel()
225 sel->r.height = clamp(sel->r.height & ~1U, IPU_ISYS_MIN_HEIGHT, in ipu7_isys_csi2_set_sel()
227 *crop = sel->r; in ipu7_isys_csi2_set_sel()
237 sd->name, sel->r.left, sel->r.top, sel->r.width, sel->r.height, in ipu7_isys_csi2_set_sel()
255 sel->pad, in ipu7_isys_csi2_get_sel()
260 crop = v4l2_subdev_state_get_crop(state, sel->pad, sel->stream); in ipu7_isys_csi2_get_sel()
267 sel->r.left = 0; in ipu7_isys_csi2_get_sel()
268 sel->r.top = 0; in ipu7_isys_csi2_get_sel()
[all …]
/drivers/clk/qcom/
A Dclk-krait.c39 regval |= (sel & mux->mask) << mux->shift; in __krait_mux_set_sel()
42 regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); in __krait_mux_set_sel()
66 u32 sel; in krait_mux_set_parent() local
68 sel = clk_mux_index_to_val(mux->parent_map, 0, index); in krait_mux_set_parent()
69 mux->en_mask = sel; in krait_mux_set_parent()
72 __krait_mux_set_sel(mux, sel); in krait_mux_set_parent()
82 u32 sel; in krait_mux_get_parent() local
84 sel = krait_get_l2_indirect_reg(mux->offset); in krait_mux_get_parent()
85 sel >>= mux->shift; in krait_mux_get_parent()
86 sel &= mux->mask; in krait_mux_get_parent()
[all …]
/drivers/accessibility/speakup/
A Dselection.c21 struct tiocl_selection sel; member
31 struct tiocl_selection sel; in __speakup_set_selection() local
33 sel = ssw->sel; in __speakup_set_selection()
51 set_selection_kernel(&sel, tty); in __speakup_set_selection()
81 speakup_sel_work.sel.xs = spk_xs + 1; in speakup_set_selection()
82 speakup_sel_work.sel.ys = spk_ys + 1; in speakup_set_selection()
83 speakup_sel_work.sel.xe = spk_xe + 1; in speakup_set_selection()
84 speakup_sel_work.sel.ye = spk_ye + 1; in speakup_set_selection()
85 speakup_sel_work.sel.sel_mode = TIOCL_SELCHAR; in speakup_set_selection()
/drivers/media/tuners/
A Dmt20xx.c121 if(s>1890) sel=0; in mt2032_compute_freq()
122 else if(s>1720) sel=1; in mt2032_compute_freq()
123 else if(s>1530) sel=2; in mt2032_compute_freq()
125 else sel=4; // >1090 in mt2032_compute_freq()
132 else sel=4; // >1090 in mt2032_compute_freq()
134 *ret_sel=sel; in mt2032_compute_freq()
220 if(sel==0) in mt2032_optimize_vco()
222 else sel--; in mt2032_optimize_vco()
225 if(sel<4) in mt2032_optimize_vco()
226 sel++; in mt2032_optimize_vco()
[all …]
/drivers/clk/imx/
A Dclk-imx35.c33 unsigned char arm, ahb, sel; member
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 4, .ahb = 1, .sel = 0},
44 { .arm = 1, .ahb = 5, .sel = 0},
45 { .arm = 1, .ahb = 8, .sel = 0},
[all …]
/drivers/watchdog/
A Dbd96801_wdt.c114 *sel = i; in find_closest_fast()
123 int sel; in find_closest_slow_by_fast() local
125 for (sel = 0; sel < ARRAY_SIZE(multipliers) && in find_closest_slow_by_fast()
126 multipliers[sel] * fast_val < *target; sel++) in find_closest_slow_by_fast()
129 if (sel == ARRAY_SIZE(multipliers)) in find_closest_slow_by_fast()
132 *slowsel = sel; in find_closest_slow_by_fast()
133 *target = multipliers[sel] * fast_val; in find_closest_slow_by_fast()
241 unsigned int val, sel, fast; in bd96801_set_heartbeat_from_hw() local
257 sel = FIELD_GET(BD96801_WD_TMO_SHORT_MASK, val); in bd96801_set_heartbeat_from_hw()
258 fast = FASTNG_MIN << sel; in bd96801_set_heartbeat_from_hw()
[all …]
/drivers/net/ethernet/chelsio/cxgb4/
A Dcxgb4_tc_u32.c56 off = cls->knode.sel->keys[i].off; in fill_match_fields()
57 val = cls->knode.sel->keys[i].val; in fill_match_fields()
58 mask = cls->knode.sel->keys[i].mask; in fill_match_fields()
62 if (!cls->knode.sel->keys[i].offmask) in fill_match_fields()
66 if (cls->knode.sel->keys[i].offmask) in fill_match_fields()
245 if (next[i].sel.offoff != cls->knode.sel->offoff || in cxgb4_config_knode()
246 next[i].sel.offshift != cls->knode.sel->offshift || in cxgb4_config_knode()
247 next[i].sel.offmask != cls->knode.sel->offmask || in cxgb4_config_knode()
248 next[i].sel.off != cls->knode.sel->off) in cxgb4_config_knode()
256 off = cls->knode.sel->keys[j].off; in cxgb4_config_knode()
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