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Searched refs:set_bits (Results 1 – 25 of 40) sorted by relevance

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/drivers/gpu/drm/xe/
A Dxe_reg_sr.c57 if (e1->clr_bits & e2->clr_bits || e1->set_bits & e2->set_bits || in compatible_entries()
58 e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits) in compatible_entries()
89 pentry->set_bits |= e->set_bits; in xe_reg_sr_add()
111 idx, e->clr_bits, e->set_bits, in xe_reg_sr_add()
157 val |= entry->set_bits; in apply_one_mmio()
213 reg, entry->clr_bits, entry->set_bits, in xe_reg_sr_dump()
A Dxe_rtp.h244 .clr_bits = ~0u, .set_bits = (val_), \
262 .clr_bits = val_, .set_bits = val_, \
280 .clr_bits = val_, .set_bits = 0, \
297 .clr_bits = mask_bits_, .set_bits = val_, \
302 .clr_bits = (mask_bits_), .set_bits = (val_), \
317 .set_bits = val_, \
A Dxe_reg_whitelist.c108 .set_bits = entry->reg.addr | entry->set_bits, in whitelist_apply_to_hwe()
156 u32 val = entry->set_bits; in xe_reg_whitelist_print_entry()
A Dxe_reg_sr_types.h17 u32 set_bits; member
A Dxe_rtp_types.h31 u32 set_bits; member
A Dxe_rtp.c178 .set_bits = action->set_bits, in rtp_add_sr_entry()
A Dxe_gt.c247 val |= entry->set_bits; in emit_wa_job()
271 *cs++ = entry->set_bits; in emit_wa_job()
288 entry->reg.addr, entry->clr_bits, entry->set_bits); in emit_wa_job()
/drivers/media/platform/ti/omap3isp/
A Disp.h329 u32 reg, u32 set_bits) in isp_reg_set() argument
333 isp_reg_writel(isp, v | set_bits, mmio_range, reg); in isp_reg_set()
348 u32 reg, u32 clr_bits, u32 set_bits) in isp_reg_clr_set() argument
352 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg); in isp_reg_clr_set()
/drivers/gpu/drm/sprd/
A Dsprd_dpu.h75 dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits) in dpu_reg_set() argument
79 writel(bits | set_bits, ctx->base + offset); in dpu_reg_set()
/drivers/tty/serial/
A Dip22zilog.c545 unsigned char set_bits, clear_bits; in ip22zilog_set_mctrl() local
547 set_bits = clear_bits = 0; in ip22zilog_set_mctrl()
550 set_bits |= RTS; in ip22zilog_set_mctrl()
554 set_bits |= DTR; in ip22zilog_set_mctrl()
559 up->curregs[R5] |= set_bits; in ip22zilog_set_mctrl()
655 unsigned char set_bits, clear_bits, new_reg; in ip22zilog_break_ctl() local
658 set_bits = clear_bits = 0; in ip22zilog_break_ctl()
661 set_bits |= SND_BRK; in ip22zilog_break_ctl()
667 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in ip22zilog_break_ctl()
A Dpmac_zilog.c516 unsigned char set_bits, clear_bits; in pmz_set_mctrl() local
525 set_bits = clear_bits = 0; in pmz_set_mctrl()
529 set_bits |= RTS; in pmz_set_mctrl()
534 set_bits |= DTR; in pmz_set_mctrl()
539 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
544 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
664 unsigned char set_bits, clear_bits, new_reg; in pmz_break_ctl() local
667 set_bits = clear_bits = 0; in pmz_break_ctl()
670 set_bits |= SND_BRK; in pmz_break_ctl()
676 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
A Dsunzilog.c646 unsigned char set_bits, clear_bits; in sunzilog_set_mctrl() local
648 set_bits = clear_bits = 0; in sunzilog_set_mctrl()
651 set_bits |= RTS; in sunzilog_set_mctrl()
655 set_bits |= DTR; in sunzilog_set_mctrl()
660 up->curregs[R5] |= set_bits; in sunzilog_set_mctrl()
756 unsigned char set_bits, clear_bits, new_reg; in sunzilog_break_ctl() local
759 set_bits = clear_bits = 0; in sunzilog_break_ctl()
762 set_bits |= SND_BRK; in sunzilog_break_ctl()
768 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in sunzilog_break_ctl()
A Drp2.c233 u32 clr_bits, u32 set_bits) in rp2_rmw() argument
237 tmp |= set_bits; in rp2_rmw()
/drivers/hwmon/
A Dgl518sm.c299 #define set_bits(type, suffix, value, reg, mask, shift) \ macro
322 set_bits(type, suffix, value, reg, 0x00ff, 0)
324 set_bits(type, suffix, value, reg, 0xff00, 8)
328 set_bits(BOOL, fan_auto1, fan_auto1, GL518_REG_MISC, 0x08, 3);
337 set_bits(BOOL, beep_enable, beep_enable, GL518_REG_CONF, 0x04, 2);
/drivers/gpu/drm/i915/gvt/
A Dinterrupt.c348 u32 set_bits = 0; in update_upstream_irq() local
372 set_bits |= (1 << bit); in update_upstream_irq()
384 vgpu_vreg(vgpu, isr) |= set_bits; in update_upstream_irq()
391 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); in update_upstream_irq()
/drivers/gpio/
A Dgpio-thunderx.c279 u64 set_bits, clear_bits; in thunderx_gpio_set_multiple() local
283 set_bits = bits[bank] & mask[bank]; in thunderx_gpio_set_multiple()
285 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); in thunderx_gpio_set_multiple()
/drivers/net/ethernet/smsc/
A Dsmc91c92_cs.c262 #define set_bits(v, p) outw(inw(p)|(v), (p)) macro
702 set_bits(0x300, link->resource[0]->start + OSITECH_AUI_PWR); in osi_setup()
704 set_bits(0x300, link->resource[0]->start + OSITECH_RESET_ISR); in osi_setup()
736 set_bits(0x0300, dev->base_addr-0x10+OSITECH_AUI_PWR); in smc91c92_resume()
737 set_bits(0x0300, dev->base_addr-0x10+OSITECH_RESET_ISR); in smc91c92_resume()
1442 set_bits(0x0300, ioaddr-0x10+OSITECH_RESET_ISR); in smc_interrupt()
1627 set_bits(OSI_AUI_PWR, ioaddr - 0x10 + OSITECH_AUI_PWR); in smc_set_xcvr()
/drivers/net/ethernet/chelsio/cxgb3/
A Dael1002.c81 unsigned short set_bits; member
91 rv->set_bits); in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
/drivers/media/radio/si4713/
A Dsi4713.c76 #define set_bits(p, v, b, m) (((p) & ~(m)) | ((v) << (b))) macro
1203 val = set_bits(val, ctrl->val, bit, mask); in si4713_s_ctrl()
1330 p = set_bits(p, stereo, 1, 1 << 1); in si4713_s_modulator()
1331 p = set_bits(p, rds, 2, 1 << 2); in si4713_s_modulator()
/drivers/media/platform/qcom/camss/
A Dcamss-vfe-17x.c177 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) in vfe_reg_set() argument
181 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
A Dcamss-vfe-4-1.c228 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) in vfe_reg_set() argument
232 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
/drivers/firewire/
A Dcore.h65 int clear_bits, int set_bits);
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
A Dhw.c47 u8 set_bits, u8 clear_bits) in _rtl92de_set_bcn_ctrl_reg() argument
52 rtlpci->reg_bcn_ctrl_val |= set_bits; in _rtl92de_set_bcn_ctrl_reg()
/drivers/gpu/drm/xe/tests/
A Dxe_rtp_test.c337 KUNIT_EXPECT_EQ(test, sr_entry->set_bits, param->expected_set_bits); in xe_rtp_process_to_sr_tests()
/drivers/net/wireless/realtek/rtlwifi/rtl8192du/
A Dhw.c20 u8 set_bits, u8 clear_bits) in _rtl92du_set_bcn_ctrl_reg() argument
25 rtlusb->reg_bcn_ctrl_val |= set_bits; in _rtl92du_set_bcn_ctrl_reg()

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