Home
last modified time | relevance | path

Searched refs:set_mp1_state (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/
A Damd_powerplay.c910 if (hwmgr->hwmgr_func->set_mp1_state) in pp_dpm_set_mp1_state()
911 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state); in pp_dpm_set_mp1_state()
1608 .set_mp1_state = pp_dpm_set_mp1_state,
/drivers/gpu/drm/amd/pm/powerplay/inc/
A Dhwmgr.h358 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state); member
/drivers/gpu/drm/amd/pm/
A Damdgpu_dpm.c185 } else if (pp_funcs && pp_funcs->set_mp1_state) { in amdgpu_dpm_set_mp1_state()
188 ret = pp_funcs->set_mp1_state( in amdgpu_dpm_set_mp1_state()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Damdgpu_smu.h970 int (*set_mp1_state)(struct smu_context *smu, member
/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c2653 smu->ppt_funcs->set_mp1_state) in smu_set_mp1_state()
2654 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); in smu_set_mp1_state()
3878 .set_mp1_state = smu_set_mp1_state,
/drivers/gpu/drm/amd/include/
A Dkgd_pp_interface.h456 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); member
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Darcturus_ppt.c2029 .set_mp1_state = smu_cmn_set_mp1_state,
A Dsienna_cichlid_ppt.c3225 .set_mp1_state = sienna_cichlid_set_mp1_state,
A Dnavi10_ppt.c3617 .set_mp1_state = smu_cmn_set_mp1_state,
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Daldebaran_ppt.c2150 .set_mp1_state = aldebaran_set_mp1_state,
A Dsmu_v13_0_7_ppt.c2867 .set_mp1_state = smu_v13_0_7_set_mp1_state,
A Dsmu_v13_0_0_ppt.c3287 .set_mp1_state = smu_v13_0_0_set_mp1_state,
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_2_ppt.c2909 .set_mp1_state = smu_v14_0_2_set_mp1_state,
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega12_hwmgr.c2984 .set_mp1_state = vega12_set_mp1_state,
A Dvega20_hwmgr.c4443 .set_mp1_state = vega20_set_mp1_state,
A Dvega10_hwmgr.c5824 .set_mp1_state = vega10_set_mp1_state,

Completed in 92 milliseconds