| /drivers/clk/ |
| A D | clk-composite.c | 30 return mux_ops->set_parent(mux_hw, index); in clk_composite_set_parent()
84 mux_hw && mux_ops && mux_ops->set_parent) { in clk_composite_determine_rate()
195 mux_ops->set_parent(mux_hw, index); in clk_composite_set_rate_and_parent()
197 mux_ops->set_parent(mux_hw, index); in clk_composite_set_rate_and_parent()
275 if (mux_ops->set_parent) in __clk_hw_register_composite()
276 clk_composite_ops->set_parent = clk_composite_set_parent; in __clk_hw_register_composite()
310 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
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| /drivers/clk/spacemit/ |
| A D | ccu_mix.c | 209 .set_parent = ccu_mux_set_parent,
235 .set_parent = ccu_mux_set_parent,
254 .set_parent = ccu_mux_set_parent,
263 .set_parent = ccu_mux_set_parent,
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| /drivers/clk/tegra/ |
| A D | clk-periph.c | 33 return mux_ops->set_parent(mux_hw, index); in clk_periph_set_parent()
137 .set_parent = clk_periph_set_parent,
151 .set_parent = clk_periph_set_parent,
161 .set_parent = clk_periph_set_parent,
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| A D | clk-tegra-super-cclk.c | 40 return tegra_clk_super_ops.set_parent(hw, index); in cclk_super_set_parent()
120 .set_parent = cclk_super_set_parent,
128 .set_parent = cclk_super_set_parent,
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| A D | clk-super.c | 141 .set_parent = clk_super_set_parent,
201 .set_parent = clk_super_set_parent,
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| /drivers/clk/actions/ |
| A D | owl-composite.c | 159 .set_parent = owl_comp_set_parent,
176 .set_parent = owl_comp_set_parent,
206 .set_parent = owl_comp_set_parent,
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| A D | owl-mux.c | 58 .set_parent = owl_mux_set_parent,
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| /drivers/clk/ti/ |
| A D | dpll.c | 30 .set_parent = &omap3_noncore_dpll_set_parent,
53 .set_parent = &omap3_noncore_dpll_set_parent,
66 .set_parent = &omap3_noncore_dpll_set_parent,
103 .set_parent = &omap3_noncore_dpll_set_parent,
115 .set_parent = &omap3_noncore_dpll_set_parent,
127 .set_parent = &omap3_noncore_dpll_set_parent,
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| /drivers/clk/starfive/ |
| A D | clk-starfive-jh71x0.c | 259 .set_parent = jh71x0_clk_set_parent,
269 .set_parent = jh71x0_clk_set_parent,
278 .set_parent = jh71x0_clk_set_parent,
290 .set_parent = jh71x0_clk_set_parent,
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| /drivers/clk/mediatek/ |
| A D | clk-mux.c | 156 .set_parent = mtk_clk_mux_set_parent_setclr_lock,
166 .set_parent = mtk_clk_mux_set_parent_setclr_lock,
306 ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index); in mtk_clk_mux_notifier_cb()
310 ret = mux_nb->ops->set_parent(hw, mux_nb->original_index); in mtk_clk_mux_notifier_cb()
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| /drivers/clk/qcom/ |
| A D | clk-rcg2.c | 806 .set_parent = clk_rcg2_set_parent,
819 .set_parent = clk_rcg2_set_parent,
831 .set_parent = clk_rcg2_set_parent,
844 .set_parent = clk_rcg2_set_parent,
857 .set_parent = clk_rcg2_set_parent,
980 .set_parent = clk_rcg2_set_parent,
1038 .set_parent = clk_rcg2_set_parent,
1108 .set_parent = clk_rcg2_set_parent,
1199 .set_parent = clk_rcg2_set_parent,
1313 .set_parent = clk_rcg2_set_parent,
[all …]
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| A D | clk-rcg.c | 826 .set_parent = clk_rcg_set_parent,
837 .set_parent = clk_rcg_set_parent,
848 .set_parent = clk_rcg_set_parent,
859 .set_parent = clk_rcg_set_parent,
871 .set_parent = clk_rcg_set_parent,
883 .set_parent = clk_rcg_set_parent,
895 .set_parent = clk_rcg_set_parent,
907 .set_parent = clk_dyn_rcg_set_parent,
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| A D | clk-regmap-mux.c | 54 .set_parent = mux_set_parent,
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| /drivers/clk/versatile/ |
| A D | clk-sp810.c | 68 .set_parent = clk_sp810_timerclken_set_parent,
129 init.ops->set_parent(&sp810->timerclken[i].hw, 1); in clk_sp810_of_setup()
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| /drivers/clk/rockchip/ |
| A D | clk-pll.c | 210 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
245 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
444 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
480 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
693 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3399_pll_set_params()
729 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
944 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3588_pll_set_params()
978 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3588_pll_set_params()
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| /drivers/sh/clk/ |
| A D | core.c | 523 if (clk->ops->set_parent) in clk_set_parent()
524 ret = clk->ops->set_parent(clk, parent); in clk_set_parent()
580 if (likely(clkp->ops->set_parent)) in clks_core_resume()
581 clkp->ops->set_parent(clkp, in clks_core_resume()
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| /drivers/gpu/drm/mcde/ |
| A D | mcde_clk_div.c | 45 unsigned long *prate, bool set_parent) in mcde_clk_div_choose_div() argument
56 if (set_parent) in mcde_clk_div_choose_div()
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| /drivers/clk/pxa/ |
| A D | clk-pxa.h | 24 .set_parent = dummy_clk_set_parent, \
75 .set_parent = name ## _set_parent, \
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| /drivers/clk/socfpga/ |
| A D | clk-gate.c | 134 .set_parent = socfpga_clk_set_parent,
194 ops->set_parent = NULL; in socfpga_gate_init()
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| /drivers/clk/imx/ |
| A D | clk-busy.c | 143 ret = busy->mux_ops->set_parent(&busy->mux.hw, index); in clk_busy_mux_set_parent()
153 .set_parent = clk_busy_mux_set_parent,
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| /drivers/clk/sprd/ |
| A D | composite.c | 53 .set_parent = sprd_comp_set_parent,
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| A D | mux.c | 73 .set_parent = sprd_mux_set_parent,
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| /drivers/clk/at91/ |
| A D | clk-i2s-mux.c | 47 .set_parent = clk_i2s_mux_set_parent,
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| /drivers/clk/davinci/ |
| A D | da8xx-cfgchip.c | 233 .set_parent = da8xx_cfgchip_mux_clk_set_parent,
500 .set_parent = da8xx_usb0_clk48_set_parent,
570 .set_parent = da8xx_usb1_clk48_set_parent,
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| /drivers/clk/sunxi-ng/ |
| A D | ccu_mp.c | 274 .set_parent = ccu_mp_set_parent,
355 .set_parent = ccu_mp_set_parent,
|