| /drivers/clk/spacemit/ |
| A D | ccu_mix.c | 203 .set_rate = ccu_factor_set_rate,
215 .set_rate = ccu_mix_set_rate,
225 .set_rate = ccu_factor_set_rate,
245 .set_rate = ccu_mix_set_rate,
258 .set_rate = ccu_mix_set_rate,
267 .set_rate = ccu_mix_set_rate,
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| /drivers/clk/starfive/ |
| A D | clk-starfive-jh71x0.c | 236 .set_rate = jh71x0_clk_set_rate,
243 .set_rate = jh71x0_clk_frac_set_rate,
253 .set_rate = jh71x0_clk_set_rate,
279 .set_rate = jh71x0_clk_set_rate,
291 .set_rate = jh71x0_clk_set_rate,
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| /drivers/clk/ti/ |
| A D | dpll.c | 29 .set_rate = &omap3_noncore_dpll_set_rate,
52 .set_rate = &omap3_noncore_dpll_set_rate,
65 .set_rate = &omap3_noncore_dpll_set_rate,
84 .set_rate = &omap2_reprogram_dpllcore,
102 .set_rate = &omap3_noncore_dpll_set_rate,
114 .set_rate = &omap3_dpll5_set_rate,
126 .set_rate = &omap3_dpll4_set_rate,
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| /drivers/sh/clk/ |
| A D | cpg.c | 185 .set_rate = sh_clk_div_set_rate,
191 .set_rate = sh_clk_div_set_rate,
318 .set_rate = sh_clk_div_set_rate,
370 .set_rate = sh_clk_div_set_rate,
450 .set_rate = fsidiv_set_rate,
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| A D | core.c | 490 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate()
491 ret = clk->ops->set_rate(clk, rate); in clk_set_rate()
583 if (likely(clkp->ops->set_rate)) in clks_core_resume()
584 clkp->ops->set_rate(clkp, rate); in clks_core_resume()
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| /drivers/clk/actions/ |
| A D | owl-composite.c | 169 .set_rate = owl_comp_div_set_rate,
186 .set_rate = owl_comp_fact_set_rate,
198 .set_rate = owl_comp_fix_fact_set_rate,
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| /drivers/clk/mvebu/ |
| A D | clk-corediv.c | 203 .set_rate = clk_corediv_set_rate,
219 .set_rate = clk_corediv_set_rate,
232 .set_rate = clk_corediv_set_rate,
244 .set_rate = clk_corediv_set_rate,
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| /drivers/clk/ |
| A D | clk-composite.c | 174 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
194 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
198 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
296 if (rate_ops->set_rate) { in __clk_hw_register_composite()
298 clk_composite_ops->set_rate = in __clk_hw_register_composite()
310 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
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| A D | clk-scpi.c | 58 .set_rate = scpi_clk_set_rate,
128 .set_rate = scpi_dvfs_set_rate,
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| /drivers/clk/mxs/ |
| A D | clk-div.c | 57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
67 .set_rate = clk_div_set_rate,
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| /drivers/clk/qcom/ |
| A D | clk-alpha-pll.c | 1179 .set_rate = clk_alpha_pll_set_rate,
1189 .set_rate = alpha_pll_huayra_set_rate,
1199 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1543 .set_rate = alpha_pll_fabia_set_rate,
1837 .set_rate = alpha_pll_trion_set_rate,
1848 .set_rate = alpha_pll_trion_set_rate,
1907 .set_rate = clk_alpha_pll_agera_set_rate,
2123 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2308 .set_rate = clk_zonda_pll_set_rate,
2968 .set_rate = clk_zonda_pll_set_rate,
[all …]
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| A D | clk-rcg2.c | 809 .set_rate = clk_rcg2_set_rate,
822 .set_rate = clk_rcg2_set_gp_rate,
834 .set_rate = clk_rcg2_set_floor_rate,
847 .set_rate = clk_rcg2_fm_set_rate,
982 .set_rate = clk_edp_pixel_set_rate,
1040 .set_rate = clk_byte_set_rate,
1110 .set_rate = clk_byte2_set_rate,
1201 .set_rate = clk_pixel_set_rate,
1315 .set_rate = clk_gfx3d_set_rate,
1552 .set_rate = clk_rcg2_shared_set_rate,
[all …]
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| A D | clk-rcg.c | 829 .set_rate = clk_rcg_set_rate,
840 .set_rate = clk_rcg_set_floor_rate,
851 .set_rate = clk_rcg_bypass_set_rate,
862 .set_rate = clk_rcg_bypass2_set_rate,
874 .set_rate = clk_rcg_pixel_set_rate,
886 .set_rate = clk_rcg_esc_set_rate,
898 .set_rate = clk_rcg_lcc_set_rate,
910 .set_rate = clk_dyn_rcg_set_rate,
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| /drivers/clk/tegra/ |
| A D | clk-periph.c | 75 return div_ops->set_rate(div_hw, rate, parent_rate); in clk_periph_set_rate()
140 .set_rate = clk_periph_set_rate,
164 .set_rate = clk_periph_set_rate,
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| A D | clk-tegra-super-cclk.c | 46 return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); in cclk_super_set_rate()
121 .set_rate = cclk_super_set_rate,
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| /drivers/clk/sophgo/ |
| A D | clk-cv18xx-ip.c | 67 .set_rate = gate_set_rate,
291 .set_rate = div_set_rate,
380 .set_rate = bypass_div_set_rate,
499 .set_rate = mux_set_rate,
591 .set_rate = bypass_mux_set_rate,
778 .set_rate = mmux_set_rate,
886 .set_rate = aclk_set_rate,
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| /drivers/clk/st/ |
| A D | clk-flexgen.c | 185 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
186 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
188 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
189 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
203 .set_rate = flexgen_set_rate,
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| /drivers/clk/imx/ |
| A D | clk-pllv3.c | 157 .set_rate = clk_pllv3_set_rate,
214 .set_rate = clk_pllv3_sys_set_rate,
305 .set_rate = clk_pllv3_av_set_rate,
401 .set_rate = clk_pllv3_vf610_set_rate,
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| A D | clk-busy.c | 63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
73 .set_rate = clk_busy_divider_set_rate,
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| /drivers/clk/ux500/ |
| A D | clk-prcmu.c | 161 .set_rate = clk_prcmu_set_rate,
173 .set_rate = clk_prcmu_set_rate,
191 .set_rate = clk_prcmu_set_rate,
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| /drivers/clk/samsung/ |
| A D | clk-pll.c | 302 .set_rate = samsung_pll35xx_set_rate,
413 .set_rate = samsung_pll36xx_set_rate,
518 .set_rate = samsung_pll0822x_set_rate,
614 .set_rate = samsung_pll0831x_set_rate,
739 .set_rate = samsung_pll45xx_set_rate,
884 .set_rate = samsung_pll46xx_set_rate,
1097 .set_rate = samsung_pll2550xx_set_rate,
1189 .set_rate = samsung_pll2650x_set_rate,
1279 .set_rate = samsung_pll2650xx_set_rate,
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| /drivers/clk/baikal-t1/ |
| A D | ccu-div.c | 538 .set_rate = ccu_div_var_set_rate_fast,
545 .set_rate = ccu_div_var_set_rate_slow,
555 .set_rate = ccu_div_fixed_set_rate,
569 .set_rate = ccu_div_fixed_set_rate,
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| /drivers/clk/at91/ |
| A D | clk-usb.c | 181 .set_rate = at91sam9x5_clk_usb_set_rate,
219 .set_rate = at91sam9x5_clk_usb_set_rate,
388 .set_rate = at91rm9200_clk_usb_set_rate,
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| A D | clk-audio-pll.c | 432 .set_rate = clk_audio_pll_frac_set_rate,
440 .set_rate = clk_audio_pll_pad_set_rate,
448 .set_rate = clk_audio_pll_pmc_set_rate,
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| /drivers/clk/sifive/ |
| A D | fu540-prci.h | 51 .set_rate = sifive_prci_wrpll_set_rate,
|