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Searched refs:setup_intf_cfg (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_encoder_phys_wb.c233 phys_enc->hw_ctl->ops.setup_intf_cfg)) { in dpu_encoder_phys_wb_setup_ctl()
259 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_ctl()
260 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_wb_setup_ctl()
267 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_ctl()
A Ddpu_encoder_phys_cmd.c59 if (!ctl->ops.setup_intf_cfg) in _dpu_encoder_phys_cmd_update_intf_cfg()
69 ctl->ops.setup_intf_cfg(ctl, &intf_cfg); in _dpu_encoder_phys_cmd_update_intf_cfg()
423 if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { in _dpu_encoder_phys_cmd_pingpong_config()
A Ddpu_hw_ctl.h220 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, member
A Ddpu_encoder_phys_vid.c267 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_vid_setup_timing_engine()
317 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
A Ddpu_hw_ctl.c816 c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1; in dpu_hw_ctl_init()
833 c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg; in dpu_hw_ctl_init()

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