Searched refs:sig1 (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/i915/gt/ |
| A D | intel_sseu_debugfs.c | 21 u32 sig1[SS_MAX], sig2[SS_MAX]; in cherryview_sseu_device_status() local
24 sig1[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG1); in cherryview_sseu_device_status()
25 sig1[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG1); in cherryview_sseu_device_status()
32 if (sig1[ss] & CHV_SS_PG_ENABLE) in cherryview_sseu_device_status()
38 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + in cherryview_sseu_device_status()
39 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + in cherryview_sseu_device_status()
40 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + in cherryview_sseu_device_status()
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| /drivers/ptp/ |
| A D | ptp_fc3.c | 138 u8 sig1, sig2; in idtfc3_get_tdc_offset_sign() local
150 sig1 = FIELD_GET(SIG1_MUX_SEL_MASK, val); in idtfc3_get_tdc_offset_sign()
153 if ((sig1 == sig2) || ((sig1 != TIME_SYNC) && (sig2 != TIME_SYNC))) { in idtfc3_get_tdc_offset_sign()
154 dev_err(idtfc3->dev, "Invalid tdc_mux_sel sig1=%d sig2=%d", sig1, sig2); in idtfc3_get_tdc_offset_sign()
156 } else if (sig1 == TIME_SYNC) { in idtfc3_get_tdc_offset_sign()
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| /drivers/scsi/ |
| A D | wd719x.h | 211 u8 sig1; member
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| A D | wd719x.c | 763 if (header.sig1 == 'W' && header.sig2 == 'D') in wd719x_read_eeprom()
769 header.sig1, header.sig2); in wd719x_read_eeprom()
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| /drivers/pci/hotplug/ |
| A D | cpqphp.h | 169 char sig1; member
185 SIG1 = offsetof(struct hrt, sig1),
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