Searched refs:skl (Results 1 – 14 of 14) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | skl_watermark.c | 1429 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); in skl_crtc_allocate_plane_ddb()
1430 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); in skl_crtc_allocate_plane_ddb()
1504 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1571 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
2383 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw; in skl_build_pipe_wm()
2839 &old_crtc_state->wm.skl.optimal, in skl_wm_add_affected_planes()
2840 &new_crtc_state->wm.skl.optimal)) in skl_wm_add_affected_planes()
3073 memset(&crtc_state->wm.skl.optimal, 0, in skl_wm_get_hw_state()
3079 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; in skl_wm_get_hw_state()
3771 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); in skl_dbuf_sanitize()
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| A D | intel_plane.c | 815 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id], in skl_next_plane_to_commit()
817 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
822 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id]; in skl_next_plane_to_commit()
823 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_next_plane_to_commit()
932 memcpy(ddb, old_crtc_state->wm.skl.plane_ddb, in skl_crtc_planes_update_arm()
933 sizeof(old_crtc_state->wm.skl.plane_ddb)); in skl_crtc_planes_update_arm()
934 memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y, in skl_crtc_planes_update_arm()
935 sizeof(old_crtc_state->wm.skl.plane_ddb_y)); in skl_crtc_planes_update_arm()
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| A D | intel_dpll_mgr.c | 1384 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_enable()
1406 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_enable()
1431 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_hw_state()
1469 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_get_hw_state()
1742 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_wrpll_get_freq()
1813 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; in skl_ddi_hdmi_pll_dividers()
1890 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_lcpll_get_freq()
1969 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_freq()
1990 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_dump_hw_state()
1999 const struct skl_dpll_hw_state *a = &_a->skl; in skl_compare_hw_state()
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| A D | intel_dpll_mgr.h | 274 struct skl_dpll_hw_state skl; member
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| A D | intel_cursor.c | 633 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_cursor_wm()
635 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_cursor_wm()
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| A D | skl_universal_plane.c | 833 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_plane_wm()
835 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_plane_wm()
837 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_plane_wm()
838 const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; in skl_write_plane_wm()
840 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; in skl_write_plane_wm()
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| A D | intel_display_debugfs.c | 668 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; in i915_ddb_info()
674 entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; in i915_ddb_info()
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| A D | intel_bw.c | 1344 &crtc_state->wm.skl.plane_ddb[plane_id], in skl_crtc_calc_dbuf_bw()
1349 &crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_crtc_calc_dbuf_bw()
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| A D | intel_display.c | 6949 entries[pipe] = old_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
6988 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
6992 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
7003 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
7004 &old_crtc_state->wm.skl.ddb) && in skl_commit_modeset_enables()
7077 skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
7080 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
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| A D | intel_display_types.h | 898 } skl; member
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| A D | intel_dmc.c | 174 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27)
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| /drivers/platform/x86/intel/int3472/ |
| A D | Kconfig | 31 The module will be named "intel-skl-int3472".
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| /drivers/gpu/drm/i915/ |
| A D | intel_clock_gating.c | 719 CG_FUNCS(skl);
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| /drivers/gpu/drm/i915/gt/uc/ |
| A D | intel_uc_fw.c | 111 fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1))
132 fw_def(SKYLAKE, 0, huc_mmp(skl, 2, 0, 0))
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