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Searched refs:slice (Results 1 – 25 of 45) sorted by relevance

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/drivers/net/ethernet/ti/icssg/
A Dicssg_classifier.c74 #define RX_CLASS_N_REG(slice, n, reg) \ argument
80 #define RX_CLASS_GATES_N_REG(slice, n) \ argument
210 offset = offs[slice].ft1_start_len; in rx_class_ft1_set_start_len()
220 offset = FT1_N_REG(slice, n, FT1_DA0); in rx_class_ft1_set_da()
223 offset = FT1_N_REG(slice, n, FT1_DA1); in rx_class_ft1_set_da()
244 offset = offs[slice].ft1_cfg; in rx_class_ft1_cfg_set_type()
254 offset = offs[slice].rx_class_cfg1; in rx_class_sel_set_type()
335 rx_class_set_and(miig_rt, slice, n, 0); in icssg_class_disable()
337 rx_class_set_or(miig_rt, slice, n, 0); in icssg_class_disable()
375 icssg_class_disable(miig_rt, slice); in icssg_class_default()
[all …]
A Dicssg_config.c140 int slice = prueth_emac_slice(emac); in icssg_config_mii_init() local
174 if (slice) in icssg_miig_queues_init()
187 hwq_map[slice][i].queue); in icssg_miig_queues_init()
199 mp = &hwq_map[slice][j]; in icssg_miig_queues_init()
226 int slice = prueth_emac_slice(emac); in icssg_config_ipg() local
286 int slice = prueth_emac_slice(emac); in prueth_fw_offload_buffer_setup() local
291 if (slice) { in prueth_fw_offload_buffer_setup()
373 int slice = prueth_emac_slice(emac); in prueth_emac_buffer_setup() local
378 if (slice) { in prueth_emac_buffer_setup()
711 fdb_cmd->param |= (slice << 4); in icssg_fdb_setup()
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A Dicssg_prueth_sr1.c55 int slice) in icssg_config_sr1() argument
157 int slice = prueth_emac_slice(emac); in icssg_config_set_speed_sr1() local
415 int slice, ret; in prueth_emac_start() local
419 slice = prueth_emac_slice(emac); in prueth_emac_start()
420 if (slice < 0) { in prueth_emac_start()
427 ret = rproc_set_firmware(prueth->pru[slice], firmwares[slice].pru); in prueth_emac_start()
434 ret = rproc_set_firmware(prueth->rtu[slice], firmwares[slice].rtu); in prueth_emac_start()
444 rproc_shutdown(prueth->pru[slice]); in prueth_emac_start()
452 int slice; in prueth_emac_stop() local
456 slice = ICSS_SLICE0; in prueth_emac_stop()
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A Dicssg_common.c295 int ret, slice, i; in prueth_init_tx_chns() local
299 if (slice < 0) in prueth_init_tx_chns()
300 return slice; in prueth_init_tx_chns()
316 "tx%d-%d", slice, i); in prueth_init_tx_chns()
374 int i, ret = 0, slice; in prueth_init_rx_chns() local
378 if (slice < 0) in prueth_init_rx_chns()
379 return slice; in prueth_init_rx_chns()
1430 switch (slice) { in prueth_get_cores()
1474 if (prueth->txpru[slice]) in prueth_put_cores()
1477 if (prueth->rtu[slice]) in prueth_put_cores()
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A Dicssg_prueth.c149 int ret, slice; in prueth_emac_start() local
160 for (slice = 0; slice < PRUETH_NUM_MACS; slice++) { in prueth_emac_start()
161 ret = prueth_start(prueth->pru[slice], firmwares[slice].pru); in prueth_emac_start()
167 ret = prueth_start(prueth->rtu[slice], firmwares[slice].rtu); in prueth_emac_start()
174 ret = prueth_start(prueth->txpru[slice], firmwares[slice].txpru); in prueth_emac_start()
186 while (--slice >= 0) { in prueth_emac_start()
197 int slice; in prueth_emac_stop() local
199 for (slice = 0; slice < PRUETH_NUM_MACS; slice++) { in prueth_emac_stop()
210 int slice; in prueth_emac_common_start() local
227 for (slice = 0; slice < PRUETH_NUM_MACS; slice++) { in prueth_emac_common_start()
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A Dicssg_prueth.h404 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac);
406 void icssg_class_disable(struct regmap *miig_rt, int slice);
407 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti,
409 void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice);
410 void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice,
412 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr);
417 int slice);
491 int prueth_get_cores(struct prueth *prueth, int slice, bool is_sr1);
492 void prueth_put_cores(struct prueth *prueth, int slice);
A Dicssg_stats.c22 int slice = prueth_emac_slice(emac); in emac_update_hardware_stats() local
23 u32 base = stats_base[slice]; in emac_update_hardware_stats()
38 base = stats_base[slice ^ 1]; in emac_update_hardware_stats()
57 slice * sizeof(u32); in emac_update_hardware_stats()
A Dicssg_mii_cfg.c48 int slice = prueth_emac_slice(emac); in icssg_update_rgmii_cfg() local
51 gig_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_GIG_EN_MII0 : in icssg_update_rgmii_cfg()
57 inband_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_INBAND_EN_MII0 : in icssg_update_rgmii_cfg()
63 full_duplex_mask = (slice == ICSS_MII0) ? RGMII_CFG_FULL_DUPLEX_MII0 : in icssg_update_rgmii_cfg()
/drivers/staging/media/sunxi/cedrus/
A Dcedrus_vp8.c554 if (!V4L2_VP8_FRAME_IS_KEY_FRAME(slice)) in cedrus_read_header()
559 if (!V4L2_VP8_FRAME_IS_KEY_FRAME(slice)) in cedrus_read_header()
608 prob_table[0x101d] = slice->prob_intra; in cedrus_vp8_update_probs()
609 prob_table[0x101e] = slice->prob_last; in cedrus_vp8_update_probs()
610 prob_table[0x101f] = slice->prob_gf; in cedrus_vp8_update_probs()
671 reg = slice->first_part_size * 8; in cedrus_vp8_setup()
707 switch (slice->version) { in cedrus_vp8_setup()
752 cedrus_read_header(dev, slice); in cedrus_vp8_setup()
822 if (slice->lf.level) { in cedrus_vp8_setup()
826 !V4L2_VP8_FRAME_IS_KEY_FRAME(slice); in cedrus_vp8_setup()
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A Dcedrus_h264.c240 slice->ref_pic_list0, in cedrus_write_ref_list0()
241 slice->num_ref_idx_l0_active_minus1 + 1, in cedrus_write_ref_list0()
251 slice->ref_pic_list1, in cedrus_write_ref_list1()
252 slice->num_ref_idx_l1_active_minus1 + 1, in cedrus_write_ref_list1()
389 cedrus_skip_bits(dev, slice->header_bit_size); in cedrus_set_params()
394 if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || in cedrus_set_params()
396 (slice->slice_type == V4L2_H264_SLICE_TYPE_B)) in cedrus_set_params()
399 if (slice->slice_type == V4L2_H264_SLICE_TYPE_B) in cedrus_set_params()
444 reg |= (slice->slice_type & 0xf) << 8; in cedrus_set_params()
445 reg |= slice->cabac_init_idc & 0x3; in cedrus_set_params()
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/drivers/misc/eeprom/
A Dmax6875.c60 if (slice >= USER_EEPROM_SLICES) in max6875_update_slice()
65 buf = &data->data[slice << SLICE_BITS]; in max6875_update_slice()
67 if (!(data->valid & (1 << slice)) || in max6875_update_slice()
68 time_after(jiffies, data->last_updated[slice])) { in max6875_update_slice()
72 data->valid &= ~(1 << slice); in max6875_update_slice()
74 addr = USER_EEPROM_BASE + (slice << SLICE_BITS); in max6875_update_slice()
99 data->last_updated[slice] = jiffies; in max6875_update_slice()
100 data->valid |= (1 << slice); in max6875_update_slice()
112 int slice, max_slice; in max6875_read() local
116 for (slice = (off >> SLICE_BITS); slice <= max_slice; slice++) in max6875_read()
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/drivers/accel/qaic/
A Dqaic_data.c163 slice->bo->total_slice_nents -= slice->nents; in free_slice()
164 list_del(&slice->slice); in free_slice()
167 kfree(slice->sgt); in free_slice()
169 kfree(slice); in free_slice()
401 slice = kmalloc(sizeof(*slice), GFP_KERNEL); in qaic_map_one_slice()
402 if (!slice) { in qaic_map_one_slice()
417 slice->bo = bo; in qaic_map_one_slice()
428 list_add_tail(&slice->slice, &bo->slices); in qaic_map_one_slice()
435 kfree(slice); in qaic_map_one_slice()
910 list_for_each_entry_safe(slice, temp, &bo->slices, slice) in qaic_free_slices_bo()
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/drivers/gpu/drm/omapdrm/
A Dtcm.h222 static inline void tcm_slice(struct tcm_area *parent, struct tcm_area *slice) in tcm_slice() argument
224 *slice = *parent; in tcm_slice()
227 if (slice->tcm && !slice->is2d && in tcm_slice()
228 slice->p0.y != slice->p1.y && in tcm_slice()
229 (slice->p0.x || (slice->p1.x != slice->tcm->width - 1))) { in tcm_slice()
231 slice->p1.x = slice->tcm->width - 1; in tcm_slice()
232 slice->p1.y = (slice->p0.x) ? slice->p0.y : slice->p1.y - 1; in tcm_slice()
235 parent->p0.y = slice->p1.y + 1; in tcm_slice()
/drivers/hid/surface-hid/
A Dsurface_hid.c45 struct surface_hid_buffer_slice *slice; in ssam_hid_get_descriptor() local
70 slice = (struct surface_hid_buffer_slice *)buffer; in ssam_hid_get_descriptor()
71 slice->entry = entry; in ssam_hid_get_descriptor()
72 slice->end = 0; in ssam_hid_get_descriptor()
77 while (!slice->end && offset < len) { in ssam_hid_get_descriptor()
78 put_unaligned_le32(offset, &slice->offset); in ssam_hid_get_descriptor()
79 put_unaligned_le32(length, &slice->length); in ssam_hid_get_descriptor()
84 sizeof(*slice)); in ssam_hid_get_descriptor()
88 offset = get_unaligned_le32(&slice->offset); in ssam_hid_get_descriptor()
89 length = get_unaligned_le32(&slice->length); in ssam_hid_get_descriptor()
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/drivers/gpu/drm/i915/
A Di915_sysfs.c68 int slice = (int)(uintptr_t)attr->private; in i915_l3_read() local
80 if (i915->l3_parity.remap_info[slice]) in i915_l3_read()
82 i915->l3_parity.remap_info[slice] + offset / sizeof(u32), in i915_l3_read()
96 int slice = (int)(uintptr_t)attr->private; in i915_l3_write() local
114 if (i915->l3_parity.remap_info[slice]) { in i915_l3_write()
116 remap_info = i915->l3_parity.remap_info[slice]; in i915_l3_write()
118 i915->l3_parity.remap_info[slice] = remap_info; in i915_l3_write()
126 ctx->remap_slice |= BIT(slice); in i915_l3_write()
/drivers/gpu/drm/i915/gt/
A Dintel_gt_regs.h71 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) argument
76 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) argument
453 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) argument
454 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) argument
514 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) argument
518 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ argument
522 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) argument
523 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ argument
525 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) argument
609 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) argument
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A Dintel_sseu.h122 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, in intel_sseu_has_subslice() argument
125 if (slice >= sseu->max_slices || in intel_sseu_has_subslice()
132 return sseu->subslice_mask.hsw[slice] & BIT(subslice); in intel_sseu_has_subslice()
156 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
A Dintel_sseu.c38 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice) in intel_sseu_get_hsw_subslices() argument
41 if (WARN_ON(slice >= sseu->max_slices)) in intel_sseu_get_hsw_subslices()
44 return sseu->subslice_mask.hsw[slice]; in intel_sseu_get_hsw_subslices()
47 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, in sseu_get_eus() argument
51 WARN_ON(slice > 0); in sseu_get_eus()
54 return sseu->eu_mask.hsw[slice][subslice]; in sseu_get_eus()
58 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, in sseu_set_eus() argument
63 GEM_WARN_ON(slice > 0); in sseu_set_eus()
66 sseu->eu_mask.hsw[slice][subslice] = eu_mask; in sseu_set_eus()
A Dintel_workarounds.c1118 unsigned int slice, subslice; in gen9_wa_init_mcr() local
1134 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
1135 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); in gen9_wa_init_mcr()
1136 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); in gen9_wa_init_mcr()
1144 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); in gen9_wa_init_mcr()
1246 unsigned int slice, unsigned int subslice) in __set_mcr_steering() argument
1266 unsigned int slice, unsigned int subslice) in __add_mcr_wa() argument
1270 gt->default_steering.groupid = slice; in __add_mcr_wa()
1311 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr() local
1367 slice = __ffs(slice_mask); in xehp_init_mcr()
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/drivers/hte/
A Dhte-tegra194.c109 int slice; member
371 if (m[eid].slice == NV_AON_SLICE_INVALID) in tegra_hte_map_to_line_id()
459 u32 slice, sl_bit_shift, line_bit, val, reg; in tegra_hte_en_dis_common() local
476 slice = line_id >> sl_bit_shift; in tegra_hte_en_dis_common()
478 reg = (slice << sl_bit_shift) + HTE_SLICE0_TETEN; in tegra_hte_en_dis_common()
480 spin_lock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
483 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
495 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
498 line_id, slice, line_bit, reg); in tegra_hte_en_dis_common()
615 slice = (src >> HTE_TESRC_SLICE_SHIFT) & in tegra_hte_read_fifo()
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/drivers/net/ethernet/myricom/myri10ge/
A Dmyri10ge.c1796 int slice; in myri10ge_get_ethtool_stats() local
1837 for (slice = 0; slice < mgp->num_slices; slice++) { in myri10ge_get_ethtool_stats()
1839 data[i++] = slice; in myri10ge_get_ethtool_stats()
1948 cmd.data0 = slice; in myri10ge_allocate_rings()
1951 cmd.data0 = slice; in myri10ge_allocate_rings()
2246 cmd.data0 = slice; in myri10ge_get_txrx()
2252 cmd.data0 = slice; in myri10ge_get_txrx()
2278 if (slice != 0) in myri10ge_set_stats()
2389 for (slice = 0; slice < mgp->num_slices; slice++) { in myri10ge_open()
2458 while (slice) { in myri10ge_open()
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/drivers/gpu/drm/i915/display/
A Dintel_bw.c1269 enum dbuf_slice slice; in intel_dbuf_bw_changed() local
1271 for_each_dbuf_slice(display, slice) { in intel_dbuf_bw_changed()
1272 if (old_dbuf_bw->max_bw[slice] != new_dbuf_bw->max_bw[slice] || in intel_dbuf_bw_changed()
1273 old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice]) in intel_dbuf_bw_changed()
1311 enum dbuf_slice slice; in skl_plane_calc_dbuf_bw() local
1317 for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) { in skl_plane_calc_dbuf_bw()
1318 dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate); in skl_plane_calc_dbuf_bw()
1319 dbuf_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw()
1360 enum dbuf_slice slice; in intel_bw_dbuf_min_cdclk() local
1362 for_each_dbuf_slice(display, slice) { in intel_bw_dbuf_min_cdclk()
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A Dskl_watermark_regs.h58 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ argument
/drivers/gpu/drm/xe/
A Dxe_trace.h431 TP_PROTO(u8 slice, u8 subslice,
434 TP_ARGS(slice, subslice,
438 TP_STRUCT__entry(__field(u8, slice)
446 TP_fast_assign(__entry->slice = slice;
455 __entry->slice, __entry->subslice,
/drivers/crypto/intel/qat/qat_common/
A Dadf_tl_debugfs.h42 #define ADF_TL_SLICE_REG_OFF(slice, reg, qat_gen) \ argument
43 (ADF_TL_DEV_REG_OFF(slice##_slices[0], qat_gen) + \

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