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Searched refs:slice_chunk_size (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc_dpi.c66 to->slice_chunk_size = from->slice_chunk_size; in copy_pps_fields()
115 (uint32_t)(div_u64(((uint64_t)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1)), in dscc_compute_dsc_parameters()
/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c155 pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); in drm_dsc_pps_payload_pack()
1329 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()
1338 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()
1356 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()
1485 cfg->slice_count, cfg->slice_width, cfg->slice_height, cfg->slice_chunk_size); in drm_dsc_dump_config_main_params()
/drivers/gpu/drm/msm/
A Dmsm_dsc_helper.h24 return dsc->slice_count * dsc->slice_chunk_size; in msm_dsc_get_bytes_per_line()
/drivers/gpu/drm/i915/display/
A Dintel_vdsc_regs.h186 #define DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_M… argument
187 slice_chunk_size)
A Dintel_vdsc.c544 pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | in intel_dsc_pps_configure()
964 vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp); in intel_dsc_get_pps_config()
A Dintel_display.c5411 PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size); in intel_pipe_config_compare()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc.c84 data = dsc->slice_chunk_size << 16; in dpu_hw_dsc_config()
A Ddpu_hw_dsc_1_2.c168 (dsc->slice_chunk_size) & 0xffff); in dpu_hw_dsc_config_1_2()
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c299 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); in dsc_log_pps()
535 reg_vals->pps.slice_chunk_size = 0; in dsc_init_reg_values()
640 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); in dsc_write_to_registers()
/drivers/gpu/drm/msm/dsi/
A Ddsi_host.c912 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; in dsi_update_dsc_timing()
913 bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ in dsi_update_dsc_timing()
950 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); in dsi_update_dsc_timing()
1077 wc = msm_host->dsc->slice_chunk_size + 1; in dsi_timing_setup()
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c262 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); in dsc_write_to_registers()

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