| /drivers/gpu/drm/msm/ |
| A D | msm_dsc_helper.h | 24 return dsc->slice_count * dsc->slice_chunk_size; in msm_dsc_get_bytes_per_line()
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| /drivers/crypto/intel/qat/qat_common/ |
| A D | adf_admin.c | 504 struct icp_qat_fw_init_admin_slice_cnt *slice_count) in adf_send_admin_tl_start() argument
522 memcpy(slice_count, &resp.slices, sizeof(*slice_count)); in adf_send_admin_tl_start()
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| A D | adf_telemetry.c | 44 static int validate_tl_slice_counters(struct icp_qat_fw_init_admin_slice_cnt *slice_count, in validate_tl_slice_counters() argument
47 u8 *sl_counter = (u8 *)slice_count; in validate_tl_slice_counters()
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| A D | adf_admin.h | 28 struct icp_qat_fw_init_admin_slice_cnt *slice_count);
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hw_dsc_1_2.c | 112 num_active_slice_per_enc = dsc->slice_count; in dpu_hw_dsc_config_1_2()
114 num_active_slice_per_enc = dsc->slice_count / 2; in dpu_hw_dsc_config_1_2()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_wrapper.h | 89 int slice_count);
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| /drivers/gpu/drm/panel/ |
| A D | panel-lg-sw43408.c | 282 ctx->dsc.slice_count = 2; in sw43408_probe()
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| A D | panel-novatek-nt37801.c | 296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
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| A D | panel-samsung-s6e3ha8.c | 297 priv->dsc.slice_count = 1440 / priv->dsc.slice_width; in s6e3ha8_amb577px01_wqhd_probe()
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| A D | panel-visionox-r66451.c | 274 dsc->slice_count = 2; in visionox_r66451_probe()
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| A D | panel-raydium-rm692e5.c | 329 ctx->dsc.slice_count = 1224 / ctx->dsc.slice_width; in rm692e5_probe()
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| A D | panel-visionox-rm692e5.c | 402 ctx->dsc.slice_count = 1080 / ctx->dsc.slice_width; in visionox_rm692e5_probe()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | resource.h | 370 int slice_count);
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 1113 int slice_count; member
1120 int slice_count; member
1133 table->odm_combines[i].slice_count += diff; in update_slice_table_for_stream()
1141 table->odm_combines[i].slice_count = diff; in update_slice_table_for_stream()
1154 table->mpc_combines[i].slice_count += diff; in update_slice_table_for_plane()
1163 table->mpc_combines[i].slice_count = diff; in update_slice_table_for_plane()
1276 table->odm_combines[i].slice_count); in update_pipes_with_slice_table()
1282 table->mpc_combines[i].slice_count); in update_pipes_with_slice_table()
1364 if (slice_table.mpc_combines[i].slice_count > 1) in should_apply_odm_power_optimization()
1368 if (slice_table.odm_combines[i].slice_count > 1) in should_apply_odm_power_optimization()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 2300 int stream_idx, int slice_idx, int plane_idx, int slice_count, in resource_log_pipe() argument
2334 } else if (slice_idx == slice_count - 1) { in resource_log_pipe()
2353 int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count; in resource_log_pipe_for_stream() local
2357 slice_count = resource_get_opp_heads_for_otg_master(otg_master, in resource_log_pipe_for_stream()
2359 for (slice_idx = 0; slice_idx < slice_count; slice_idx++) { in resource_log_pipe_for_stream()
2373 plane_idx, slice_count, in resource_log_pipe_for_stream()
2379 slice_count, true); in resource_log_pipe_for_stream()
5588 int slice_count = resource_get_opp_heads_for_otg_master(otg_master, in resource_calculate_det_for_stream() local
5591 for (int slice_idx = 0; slice_idx < slice_count; slice_idx++) { in resource_calculate_det_for_stream()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_vdsc.c | 282 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
1023 crtc_state->dsc.slice_count, in intel_vdsc_dump_state()
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| A D | intel_bios.c | 3491 crtc_state->dsc.slice_count = 4; in fill_dsc()
3493 crtc_state->dsc.slice_count = 2; in fill_dsc()
3500 crtc_state->dsc.slice_count = 1; in fill_dsc()
3504 crtc_state->dsc.slice_count != 0) in fill_dsc()
3508 crtc_state->dsc.slice_count); in fill_dsc()
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| A D | intel_dp.c | 2401 pipe_config->dsc.slice_count = in intel_dp_dsc_compute_config()
2404 if (!pipe_config->dsc.slice_count) { in intel_dp_dsc_compute_config()
2407 pipe_config->dsc.slice_count); in intel_dp_dsc_compute_config()
2424 pipe_config->dsc.slice_count = dsc_dp_slice_count; in intel_dp_dsc_compute_config()
2434 pipe_config->dsc.slice_count == 12) in intel_dp_dsc_compute_config()
2436 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) in intel_dp_dsc_compute_config()
2456 pipe_config->dsc.slice_count); in intel_dp_dsc_compute_config()
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| A D | intel_display_types.h | 1273 u8 slice_count; member
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| A D | icl_dsi.c | 1606 if (crtc_state->dsc.slice_count > 1) in gen11_dsi_dsc_compute_config()
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| /drivers/gpu/drm/display/ |
| A D | drm_dsc_helper.c | 1485 cfg->slice_count, cfg->slice_width, cfg->slice_height, cfg->slice_chunk_size); in drm_dsc_dump_config_main_params()
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| A D | drm_dp_helper.c | 4487 int slice_count = dsc_slice_count ? : 1; in drm_dp_link_symbol_cycles() local
4488 int slice_pixels = DIV_ROUND_UP(pixels, slice_count); in drm_dp_link_symbol_cycles()
4499 return slice_count * (slice_data_cycles + slice_eoc_cycles); in drm_dp_link_symbol_cycles()
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| /drivers/media/platform/st/sti/hva/ |
| A D | hva-h264.c | 390 u32 slice_count; member
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 1649 int slice_count = resource_get_opp_heads_for_otg_master(otg_master, in dcn401_wait_for_det_buffer_update_under_otg_master() local
1652 for (int slice_idx = 0; slice_idx < slice_count; slice_idx++) { in dcn401_wait_for_det_buffer_update_under_otg_master()
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| /drivers/gpu/drm/msm/dsi/ |
| A D | dsi_host.c | 910 slice_per_intf = dsc->slice_count; in dsi_update_dsc_timing()
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