| /drivers/gpu/drm/amd/display/dc/dsc/ |
| A D | rc_calc.c | 48 int slice_height = pps->slice_height; in calc_rc_params() local
60 slice_width, slice_height, in calc_rc_params()
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| A D | dc_dsc.c | 1065 int slice_height; in setup_dsc_config() local
1238 slice_height = min(policy.min_slice_height, pic_height); in setup_dsc_config()
1240 slice_height = min((int)(options->dsc_min_slice_height_override), pic_height); in setup_dsc_config()
1242 while (slice_height < pic_height && (pic_height % slice_height != 0 || in setup_dsc_config()
1243 slice_height % options->slice_height_granularity != 0 || in setup_dsc_config()
1244 (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0))) in setup_dsc_config()
1245 slice_height++; in setup_dsc_config()
1248 is_dsc_possible = (slice_height % 2 == 0); in setup_dsc_config()
1253 if (slice_height > 0) { in setup_dsc_config()
1254 dsc_cfg->num_slices_v = pic_height / slice_height; in setup_dsc_config()
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| A D | rc_calc_dpi.c | 35 to->slice_height = from->slice_height; in copy_pps_fields()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_vdsc.c | 95 if (vdsc_cfg->slice_height >= 8) in calculate_rc_params()
97 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100; in calculate_rc_params()
99 first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); in calculate_rc_params()
116 if (vdsc_cfg->slice_height >= 8) in calculate_rc_params()
120 2 * (vdsc_cfg->slice_height - 1); in calculate_rc_params()
124 vdsc_cfg->slice_height - 1); in calculate_rc_params()
245 if (vdsc_cfg->slice_height > 4095) in intel_dsc_slice_dimensions_valid()
252 if (vdsc_cfg->slice_height % 2) in intel_dsc_slice_dimensions_valid()
254 if (vdsc_cfg->slice_height > 4094) in intel_dsc_slice_dimensions_valid()
500 pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) | in intel_dsc_pps_configure()
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| A D | intel_vdsc_regs.h | 116 #define DSC_PPS3_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_heig… argument
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| A D | intel_dp.c | 1862 int slice_height; in intel_dp_get_slice_height() local
1870 for (slice_height = 108; slice_height <= vactive; slice_height += 2) in intel_dp_get_slice_height()
1871 if (vactive % slice_height == 0) in intel_dp_get_slice_height()
1872 return slice_height; in intel_dp_get_slice_height()
1898 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); in intel_dp_dsc_compute_params()
3994 int slice_height; in intel_dp_pcon_dsc_configure() local
4015 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); in intel_dp_pcon_dsc_configure()
4016 if (!slice_height) in intel_dp_pcon_dsc_configure()
4031 pps_param[0] = slice_height & 0xFF; in intel_dp_pcon_dsc_configure()
4032 pps_param[1] = slice_height >> 8; in intel_dp_pcon_dsc_configure()
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| A D | intel_hdmi.c | 3120 int slice_height; in intel_hdmi_dsc_get_slice_height() local
3129 for (slice_height = 96; slice_height <= vactive; slice_height += 2) in intel_hdmi_dsc_get_slice_height()
3130 if (vactive % slice_height == 0) in intel_hdmi_dsc_get_slice_height()
3131 return slice_height; in intel_hdmi_dsc_get_slice_height()
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| A D | icl_dsi.c | 1625 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()
1627 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()
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| A D | intel_vbt_defs.h | 1579 u16 slice_height; member
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| A D | intel_bios.c | 3522 vdsc_cfg->slice_height = dsc->slice_height; in fill_dsc()
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| /drivers/gpu/drm/display/ |
| A D | drm_dsc_helper.c | 149 pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); in drm_dsc_pps_payload_pack()
1356 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()
1383 if (vdsc_cfg->slice_height > 1) in drm_dsc_compute_rc_parameters()
1390 (vdsc_cfg->slice_height - 1)); in drm_dsc_compute_rc_parameters()
1395 groups_total = groups_per_line * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()
1485 cfg->slice_count, cfg->slice_width, cfg->slice_height, cfg->slice_chunk_size); in drm_dsc_dump_config_main_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dsc/ |
| A D | rc_calc_fpu.c | 171 int slice_height, in _do_calc_rc_params() argument
197 …rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((… in _do_calc_rc_params()
202 …rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((… in _do_calc_rc_params()
208 …rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((… in _do_calc_rc_params()
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| A D | rc_calc_fpu.h | 87 int slice_height,
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| A D | dcn20_dsc.c | 297 DC_LOG_DSC("\tslice_height %d", pps->slice_height); in dsc_log_pps()
412 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; in dsc_prepare_config()
414 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); in dsc_prepare_config()
415 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { in dsc_prepare_config()
539 reg_vals->pps.slice_height = 0; in dsc_init_reg_values()
648 SLICE_HEIGHT, reg_vals->pps.slice_height); in dsc_write_to_registers()
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| /drivers/gpu/drm/amd/display/modules/power/ |
| A D | power_helpers.c | 948 uint16_t slice_height; in psr_su_set_dsc_slice_height() local
964 slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; in psr_su_set_dsc_slice_height()
965 config->dsc_slice_height = slice_height; in psr_su_set_dsc_slice_height()
967 if (slice_height) { in psr_su_set_dsc_slice_height()
969 (slice_height % config->su_y_granularity)) { in psr_su_set_dsc_slice_height()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_hw_dsc.c | 81 data |= dsc->slice_height; in dpu_hw_dsc_config()
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| A D | dpu_hw_dsc_1_2.c | 163 ((dsc->slice_height & 0xffff) << 16); in dpu_hw_dsc_config_1_2()
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| /drivers/gpu/drm/panel/ |
| A D | panel-lg-sw43408.c | 280 ctx->dsc.slice_height = 16; in sw43408_probe()
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| A D | panel-novatek-nt37801.c | 294 ctx->dsc.slice_height = 40; in novatek_nt37801_probe()
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| A D | panel-samsung-s6e3ha8.c | 294 priv->dsc.slice_height = 40; in s6e3ha8_amb577px01_wqhd_probe()
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| A D | panel-visionox-r66451.c | 272 dsc->slice_height = 20; in visionox_r66451_probe()
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| A D | panel-raydium-rm692e5.c | 326 ctx->dsc.slice_height = 60; in rm692e5_probe()
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| A D | panel-visionox-rm692e5.c | 400 ctx->dsc.slice_height = 20; in visionox_rm692e5_probe()
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| A D | dcn401_dsc.c | 270 SLICE_HEIGHT, reg_vals->pps.slice_height); in dsc_write_to_registers()
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| /drivers/gpu/drm/msm/dsi/ |
| A D | dsi_host.c | 2556 if (pic_height % dsc->slice_height) { in msm_dsi_host_check_dsc()
2558 pic_height, dsc->slice_height); in msm_dsi_host_check_dsc()
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