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Searched refs:slice_mask (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/i915/gt/
A Dintel_sseu.c156 sseu->slice_mask |= BIT(0); in gen11_compute_sseu_info()
172 sseu->slice_mask |= BIT(0); in xehp_compute_sseu_info()
334 sseu->slice_mask = BIT(0); in cherryview_sseu_info_init()
403 if (!(sseu->slice_mask & BIT(s))) in gen9_sseu_info_init()
582 sseu->slice_mask = BIT(0); in hsw_sseu_info_init()
586 sseu->slice_mask = BIT(0); in hsw_sseu_info_init()
782 hweight8(sseu->slice_mask), sseu->slice_mask); in intel_sseu_dump()
875 unsigned long slice_mask = 0; in intel_slicemask_from_xehp_dssmask() local
879 8 * sizeof(slice_mask)); in intel_slicemask_from_xehp_dssmask()
884 slice_mask |= BIT(i); in intel_slicemask_from_xehp_dssmask()
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A Dintel_sseu_debugfs.c36 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
87 sseu->slice_mask |= BIT(s); in gen11_sseu_device_status()
140 sseu->slice_mask |= BIT(s); in gen9_sseu_device_status()
175 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; in bdw_sseu_device_status()
177 if (sseu->slice_mask) { in bdw_sseu_device_status()
179 for (s = 0; s < fls(sseu->slice_mask); s++) in bdw_sseu_device_status()
185 for (s = 0; s < fls(sseu->slice_mask); s++) { in bdw_sseu_device_status()
201 sseu->slice_mask); in i915_print_sseu_info()
203 hweight8(sseu->slice_mask)); in i915_print_sseu_info()
A Dintel_sseu.h69 u8 slice_mask; member
102 u8 slice_mask; member
112 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
A Dintel_workarounds.c1134 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
1283 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
1311 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr() local
1342 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, in xehp_init_mcr()
1356 if (slice_mask & lncf_mask) { in xehp_init_mcr()
1357 slice_mask &= lncf_mask; in xehp_init_mcr()
1362 if (slice_mask & gt->info.mslice_mask) { in xehp_init_mcr()
1363 slice_mask &= gt->info.mslice_mask; in xehp_init_mcr()
1367 slice = __ffs(slice_mask); in xehp_init_mcr()
/drivers/gpu/drm/i915/gem/
A Di915_gem_context.c1001 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) in intel_context_set_gem()
1916 if (!user->slice_mask || !user->subslice_mask || in i915_gem_user_to_context_sseu()
1928 if (overflows_type(user->slice_mask, context->slice_mask) || in i915_gem_user_to_context_sseu()
1937 if (user->slice_mask & ~device->slice_mask) in i915_gem_user_to_context_sseu()
1946 context->slice_mask = user->slice_mask; in i915_gem_user_to_context_sseu()
1953 unsigned int hw_s = hweight8(device->slice_mask); in i915_gem_user_to_context_sseu()
1955 unsigned int req_s = hweight8(context->slice_mask); in i915_gem_user_to_context_sseu()
2516 user_sseu.slice_mask = ce->sseu.slice_mask; in get_sseu()
/drivers/crypto/intel/qat/qat_common/
A Dicp_qat_fw_loader_handle.h19 unsigned int slice_mask; member
A Dqat_hal.c801 handle->hal_handle->slice_mask = hw_data->accel_mask; in qat_hal_chip_init()
/drivers/gpu/drm/i915/
A Di915_query.c42 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in fill_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in fill_topology_info()
73 &sseu->slice_mask, slice_length)) in fill_topology_info()
A Di915_getparam.c173 value = sseu->slice_mask; in i915_getparam_ioctl()
A Di915_perf.c3171 out_sseu->slice_mask = 0x1; in get_default_sseu_config()
/drivers/gpu/drm/i915/display/
A Dskl_watermark.c408 hweight8(DISPLAY_INFO(display)->dbuf.slice_mask); in intel_dbuf_slice_size()
417 if (!slice_mask) { in skl_ddb_entry_for_slices()
423 ddb->start = (ffs(slice_mask) - 1) * slice_size; in skl_ddb_entry_for_slices()
424 ddb->end = fls(slice_mask) * slice_size; in skl_ddb_entry_for_slices()
434 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) in mbus_ddb_offset()
435 slice_mask = BIT(DBUF_S1); in mbus_ddb_offset()
437 slice_mask = BIT(DBUF_S3); in mbus_ddb_offset()
449 u8 slice_mask = 0; in skl_ddb_dbuf_slice_mask() local
462 slice_mask |= BIT(start_slice); in skl_ddb_dbuf_slice_mask()
466 return slice_mask; in skl_ddb_dbuf_slice_mask()
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A Dintel_display_device.c663 .dbuf.slice_mask = BIT(DBUF_S1),
813 .dbuf.slice_mask = BIT(DBUF_S1), \
872 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
962 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
1129 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1307 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
A Dintel_display_power.c1087 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; in gen9_dbuf_slices_update() local
1090 drm_WARN(display->drm, req_slices & ~slice_mask, in gen9_dbuf_slices_update()
1092 req_slices, slice_mask); in gen9_dbuf_slices_update()
A Dintel_display_device.h287 u8 slice_mask; member
A Dintel_display.h86 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
/drivers/gpu/drm/i915/gem/selftests/
A Di915_gem_context.c1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1226 hweight32(sseu.slice_mask), spin); in __sseu_test()
1271 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1282 pg_sseu.slice_mask = 1; in __igt_ctx_sseu()
1288 hweight32(engine->sseu.slice_mask), in __igt_ctx_sseu()
1289 hweight32(pg_sseu.slice_mask)); in __igt_ctx_sseu()
/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_ads.c900 hweight8(gt->info.sseu.slice_mask)); in __guc_ads_init()

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