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Searched refs:slice_width (Results 1 – 25 of 31) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc.c47 int slice_width = pps->slice_width; in calc_rc_params() local
60 slice_width, slice_height, in calc_rc_params()
A Drc_calc_dpi.c34 to->slice_width = from->slice_width; in copy_pps_fields()
115 (uint32_t)(div_u64(((uint64_t)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1)), in dscc_compute_dsc_parameters()
116 (uint32_t)dsc_cfg.slice_width)); /* Round-up */ in dscc_compute_dsc_parameters()
A Ddsc.h49 uint32_t slice_width; /* Slice width in pixels */ member
A Ddc_dsc.c1059 int slice_width; in setup_dsc_config() local
1229 slice_width = pic_width / num_slices_h; in setup_dsc_config()
1231 is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width; in setup_dsc_config()
/drivers/gpu/drm/amd/display/dc/dml/dsc/
A Drc_calc_fpu.c170 int slice_width, in _do_calc_rc_params() argument
217 slice_width /= 2; in _do_calc_rc_params()
219 …padding_pixels = ((slice_width % 3) != 0) ? (3 - (slice_width % 3)) * (rc->initial_xmit_delay / sl… in _do_calc_rc_params()
A Drc_calc_fpu.h86 int slice_width,
/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c152 pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); in drm_dsc_pps_payload_pack()
1325 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, in drm_dsc_compute_rc_parameters()
1329 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()
1334 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, in drm_dsc_compute_rc_parameters()
1338 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()
1485 cfg->slice_count, cfg->slice_width, cfg->slice_height, cfg->slice_chunk_size); in drm_dsc_dump_config_main_params()
/drivers/gpu/drm/panel/
A Dpanel-samsung-s6e3ha8.c295 priv->dsc.slice_width = 720; in s6e3ha8_amb577px01_wqhd_probe()
296 WARN_ON(1440 % priv->dsc.slice_width); in s6e3ha8_amb577px01_wqhd_probe()
297 priv->dsc.slice_count = 1440 / priv->dsc.slice_width; in s6e3ha8_amb577px01_wqhd_probe()
A Dpanel-novatek-nt37801.c295 ctx->dsc.slice_width = 720; in novatek_nt37801_probe()
296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
A Dpanel-raydium-rm692e5.c327 ctx->dsc.slice_width = 1224; in rm692e5_probe()
329 ctx->dsc.slice_count = 1224 / ctx->dsc.slice_width; in rm692e5_probe()
A Dpanel-visionox-rm692e5.c401 ctx->dsc.slice_width = 540; in visionox_rm692e5_probe()
402 ctx->dsc.slice_count = 1080 / ctx->dsc.slice_width; in visionox_rm692e5_probe()
A Dpanel-lg-sw43408.c281 ctx->dsc.slice_width = 540; in sw43408_probe()
A Dpanel-visionox-r66451.c273 dsc->slice_width = 540; in visionox_r66451_probe()
/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c247 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) in intel_dsc_slice_dimensions_valid()
250 if (vdsc_cfg->slice_width % 2) in intel_dsc_slice_dimensions_valid()
256 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) in intel_dsc_slice_dimensions_valid()
281 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
501 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width); in intel_dsc_pps_configure()
546 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()
915 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); in intel_dsc_get_pps_config()
A Dintel_hdmi.h56 int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
A Dintel_vdsc_regs.h115 #define DSC_PPS3_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width) argument
A Dintel_hdmi.c3171 int slice_width; in intel_hdmi_dsc_get_num_slices() local
3221 slice_width = max_slice_width; in intel_hdmi_dsc_get_num_slices()
3239 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); in intel_hdmi_dsc_get_num_slices()
3240 if (slice_width >= max_slice_width) in intel_hdmi_dsc_get_num_slices()
3242 } while (slice_width >= max_slice_width); in intel_hdmi_dsc_get_num_slices()
3261 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, in intel_hdmi_dsc_get_bpp() argument
3332 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); in intel_hdmi_dsc_get_bpp()
A Dintel_dp.c3971 int num_slices, int slice_width) in intel_dp_pcon_dsc_enc_bpp() argument
3981 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, in intel_dp_pcon_dsc_enc_bpp()
3995 int slice_width; in intel_dp_pcon_dsc_configure() local
4023 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, in intel_dp_pcon_dsc_configure()
4027 num_slices, slice_width); in intel_dp_pcon_dsc_configure()
4033 pps_param[2] = slice_width & 0xFF; in intel_dp_pcon_dsc_configure()
4034 pps_param[3] = slice_width >> 8; in intel_dp_pcon_dsc_configure()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc.c62 slice_last_group_size = (dsc->slice_width + 2) % 3; in dpu_hw_dsc_config()
80 data = dsc->slice_width << 16; in dpu_hw_dsc_config()
A Ddpu_hw_dsc_1_2.c162 data = (dsc->slice_width & 0xffff) | in dpu_hw_dsc_config_1_2()
A Ddpu_encoder.c1963 soft_slice_per_enc = enc_ip_width / dsc->slice_width; in dpu_encoder_dsc_initial_line_calc()
1979 return DIV_ROUND_UP(total_pixels, dsc->slice_width); in dpu_encoder_dsc_initial_line_calc()
2043 this_frame_slices = pic_width / dsc->slice_width; in dpu_encoder_prep_dsc()
2044 intf_ip_w = this_frame_slices * dsc->slice_width; in dpu_encoder_prep_dsc()
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c298 DC_LOG_DSC("\tslice_width %d", pps->slice_width); in dsc_log_pps()
411 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; in dsc_prepare_config()
444 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; in dsc_prepare_config()
538 reg_vals->pps.slice_width = 0; in dsc_init_reg_values()
647 SLICE_WIDTH, reg_vals->pps.slice_width, in dsc_write_to_registers()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c400 unsigned int i, slice_width; in find_shift_for_valid_cache_id_assignment() local
405 slice_width = mcache_boundaries[i]; in find_shift_for_valid_cache_id_assignment()
407 slice_width = mcache_boundaries[i] - mcache_boundaries[i - 1]; in find_shift_for_valid_cache_id_assignment()
409 if (max_shift > (int)slice_width) { in find_shift_for_valid_cache_id_assignment()
410 max_shift = slice_width; in find_shift_for_valid_cache_id_assignment()
475 int i, slice_width; in calculate_h_split_for_scaling_transform() local
483 slice_width = full_vp_width / num_pipes; in calculate_h_split_for_scaling_transform()
485 pipe_vp_x_start[i] = i * slice_width; in calculate_h_split_for_scaling_transform()
486 pipe_vp_x_end[i] = (i + 1) * slice_width - 1; in calculate_h_split_for_scaling_transform()
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c269 SLICE_WIDTH, reg_vals->pps.slice_width, in dsc_write_to_registers()
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c131 dsc_optc_cfg.slice_width); in update_dsc_on_stream()

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