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Searched refs:snps (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_ddi_buf_trans.c1016 { .snps = { 62, 0, 0 } }, /* preset 0 */
1017 { .snps = { 55, 0, 7 } }, /* preset 1 */
1018 { .snps = { 50, 0, 12 } }, /* preset 2 */
1019 { .snps = { 44, 0, 18 } }, /* preset 3 */
1020 { .snps = { 35, 0, 21 } }, /* preset 4 */
1021 { .snps = { 59, 3, 0 } }, /* preset 5 */
1022 { .snps = { 53, 3, 6 } }, /* preset 6 */
1023 { .snps = { 48, 3, 11 } }, /* preset 7 */
1024 { .snps = { 42, 5, 15 } }, /* preset 8 */
1025 { .snps = { 37, 5, 20 } }, /* preset 9 */
[all …]
A Dintel_ddi_buf_trans.h59 struct dg2_snps_phy_buf_trans snps; member
A Dintel_display_core.h558 } snps; member
A Dintel_snps_phy.c47 display->snps.phy_failed_calibration |= BIT(phy); in intel_snps_phy_wait_for_calibration()
83 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); in intel_snps_phy_set_signal_levels()
84 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); in intel_snps_phy_set_signal_levels()
85 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); in intel_snps_phy_set_signal_levels()
A Dintel_cx0_phy.c501 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), in intel_cx0_phy_set_signal_levels()
505 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), in intel_cx0_phy_set_signal_levels()
509 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), in intel_cx0_phy_set_signal_levels()
A Dintel_ddi.c5145 display->snps.phy_failed_calibration & BIT(phy)) { in intel_ddi_init()
/drivers/phy/
A DMakefile12 obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
/drivers/phy/rockchip/
A DMakefile13 obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
A DKconfig117 Enable this to support the Rockchip snps PCIe3 PHY.
/drivers/phy/qualcomm/
A DMakefile25 obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2)+= phy-qcom-snps-femto-v2.o
/drivers/net/ethernet/stmicro/stmmac/
A DKconfig46 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
51 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
/drivers/gpio/
A DMakefile55 obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o
/drivers/pinctrl/tegra/
A Dpinctrl-tegra-xusb.c789 TEGRA124_FUNCTION(snps),
/drivers/mmc/host/
A Dsdhci-pci-core.c1947 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),

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