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Searched refs:soc_bb (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/
A Ddml2_mcg_dcn4.c89 if (soc_bb->max_fclk_for_uclk_dpm_khz > 0 && in build_min_clk_table_fine_grained()
152 if (!soc_bb || !min_table) in build_min_clock_table()
155 if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2) in build_min_clock_table()
169 if (soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.dcfclk.num_clk_values && in build_min_clock_table()
170 soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.uclk.num_clk_values) in build_min_clock_table()
180 …min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppcl… in build_min_clock_table()
181 …min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dsccl… in build_min_clock_table()
182 …min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbcl… in build_min_clock_table()
183 …min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phycl… in build_min_clock_table()
189 …min_table->max_clocks_khz.dcfclk = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfcl… in build_min_clock_table()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c37 &in_out->soc_bb->clk_table.dram_config); in get_minimum_clocks_for_latency()
492 if (min_idle_us >= in_out->soc_bb->power_management_parameters.fclk_change_blackout_us) in determine_power_management_features_with_vblank_only()
578 …mming->min_clocks.dcn4x.active.uclk_khz = in_out->soc_bb->clk_table.uclk.clk_values_khz[in_out->so… in clamp_uclk_to_max()
579 …>min_clocks.dcn4x.svp_prefetch.uclk_khz = in_out->soc_bb->clk_table.uclk.clk_values_khz[in_out->so… in clamp_uclk_to_max()
580 …ramming->min_clocks.dcn4x.idle.uclk_khz = in_out->soc_bb->clk_table.uclk.clk_values_khz[in_out->so… in clamp_uclk_to_max()
585 …mming->min_clocks.dcn4x.active.fclk_khz = in_out->soc_bb->clk_table.fclk.clk_values_khz[in_out->so… in clamp_fclk_to_max()
586 …ramming->min_clocks.dcn4x.idle.fclk_khz = in_out->soc_bb->clk_table.fclk.clk_values_khz[in_out->so… in clamp_fclk_to_max()
632 if (in_out->soc_bb->no_dfs) { in map_mode_to_soc_dpm()
727 if (in_out->soc_bb->power_management_parameters.z8_min_idle_time > 0 && in dpmm_dcn4_map_mode_to_soc_dpm()
733 if (in_out->soc_bb->power_management_parameters.z8_stutter_exit_latency_us > 0 && in dpmm_dcn4_map_mode_to_soc_dpm()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/
A Ddml2_pmo_dcn3.c238 pmo->soc_bb = in_out->soc_bb; in pmo_dcn3_initialize()
548 in_out->instance->soc_bb->power_management_parameters.dram_clk_change_blackout_us && in pmo_dcn3_init_for_pstate_support()
556 in_out->instance->soc_bb->power_management_parameters.fclk_change_blackout_us && in pmo_dcn3_init_for_pstate_support()
608 …in_out->instance->soc_bb->power_management_parameters.fclk_change_blackout_us > min_reserved_vblan… in pmo_dcn3_init_for_pstate_support()
612 in_out->instance->soc_bb->power_management_parameters.fclk_change_blackout_us; in pmo_dcn3_init_for_pstate_support()
617 …in_out->instance->soc_bb->power_management_parameters.dram_clk_change_blackout_us > min_reserved_v… in pmo_dcn3_init_for_pstate_support()
621 in_out->instance->soc_bb->power_management_parameters.dram_clk_change_blackout_us; in pmo_dcn3_init_for_pstate_support()
627 …in_out->instance->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > min_res… in pmo_dcn3_init_for_pstate_support()
630 in_out->instance->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us; in pmo_dcn3_init_for_pstate_support()
A Ddml2_pmo_dcn4_fams2.c645 pmo->soc_bb = in_out->soc_bb; in pmo_dcn4_fams2_initialize()
1119 if (total_mcaches_required > pmo->soc_bb->num_dcc_mcaches) { in all_timings_support_svp()
1719 (unsigned int)math_ceil(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us / in build_fams2_meta_per_stream()
2185 …REQUIRED_RESERVED_TIME = (int)in_out->instance->soc_bb->power_management_parameters.dram_clk_chang… in pmo_dcn4_fams2_test_for_pstate_support()
2273 if (pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us > 0 && in pmo_dcn4_fams2_init_for_stutter()
2274 pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0 && in pmo_dcn4_fams2_init_for_stutter()
2275 …pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us < pmo->soc_bb->power_managemen… in pmo_dcn4_fams2_init_for_stutter()
2280 …pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us + pmo->soc_bb->power_managemen… in pmo_dcn4_fams2_init_for_stutter()
2305 if (pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us > 0) { in pmo_dcn4_fams2_init_for_stutter()
2333 if (pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us > 0 && in pmo_dcn4_fams2_test_for_stutter()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_internal_shared_types.h61 struct dml2_soc_bb *soc_bb; member
84 struct dml2_soc_bb *soc_bb; member
89 struct dml2_core_internal_soc_bb *soc_bb; member
129 struct dml2_soc_bb *soc_bb; member
139 struct soc_bounding_box_st *soc_bb; member
501 struct dml2_soc_bb *soc_bb; member
688 struct dml2_soc_bb *soc_bb; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_wrapper.c153 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
155 …in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table… in dml21_calculate_rq_and_dlg_params()
157 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispc… in dml21_calculate_rq_and_dlg_params()
160 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
162 …in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.… in dml21_calculate_rq_and_dlg_params()
164 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk… in dml21_calculate_rq_and_dlg_params()
A Ddml21_translation_helper.c55 dml_init->soc_bb = dml2_socbb_dcn401; in populate_default_dml_init_params()
56 dml_init->soc_bb.qos_parameters = dml_dcn4_variant_a_soc_qos_params; in populate_default_dml_init_params()
71 dml_init->soc_bb.dprefclk_mhz = in_dc->clk_mgr->dprefclk_khz / 1000; in override_dml_init_with_values_from_hardware_default()
92 struct dml2_soc_state_table *dml_clk_table = &dml_init->soc_bb.clk_table; in override_dml_init_with_values_from_smu()
267 struct dml2_soc_bb *dml_soc_bb = &dml_init->soc_bb; in override_dml_init_with_values_from_vbios()
268 struct dml2_soc_state_table *dml_clk_table = &dml_init->soc_bb.clk_table; in override_dml_init_with_values_from_vbios()
374 dml_init->soc_bb = config->external_socbb_ip_params->soc_bb; in override_dml_init_with_values_from_software_policy()
379 dml_init->soc_bb.power_management_parameters.stutter_exit_latency_us = in override_dml_init_with_values_from_software_policy()
383 dml_init->soc_bb.power_management_parameters.stutter_enter_plus_exit_latency_us = in override_dml_init_with_values_from_software_policy()
387 dml_init->soc_bb.power_management_parameters.dram_clk_change_blackout_us = in override_dml_init_with_values_from_software_policy()
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A Ddml21_wrapper.h70 struct dml2_soc_bb soc_bb; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c813 l->dppm_map_mode_params.soc_bb = &dml->soc_bbox; in dml2_top_soc15_check_mode_supported()
985 l->dppm_map_mode_params.soc_bb = &dml->soc_bbox; in dml2_top_soc15_build_mode_programming()
1122 memcpy(&dml->soc_bbox, &in_out->soc_bb, sizeof(struct dml2_soc_bb)); in dml2_top_soc15_initialize_instance()
1137 mcg_build_min_clk_params.soc_bb = &in_out->soc_bb; in dml2_top_soc15_initialize_instance()
1149 core_init_params.soc_bb = &in_out->soc_bb; in dml2_top_soc15_initialize_instance()
1162 pmo_init_params.soc_bb = &dml->soc_bbox; in dml2_top_soc15_initialize_instance()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.h78 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb);
A Ddcn32_fpu.c3594 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb) in dcn32_set_clock_limits() argument
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_lib.h97 const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
A Ddisplay_mode_lib.c94 const struct _vcs_dpi_soc_bounding_box_st *soc_bb, in dml_init_instance() argument
98 lib->soc = *soc_bb; in dml_init_instance()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4.c149 memcpy(&core->clean_me_up.mode_lib.soc, in_out->soc_bb, sizeof(struct dml2_soc_bb)); in core_dcn4_initialize()
529 static int lookup_uclk_dpm_index_by_freq(unsigned long uclk_freq_khz, struct dml2_soc_bb *soc_bb) in lookup_uclk_dpm_index_by_freq() argument
533 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in lookup_uclk_dpm_index_by_freq()
534 if (uclk_freq_khz == soc_bb->clk_table.uclk.clk_values_khz[i]) in lookup_uclk_dpm_index_by_freq()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_types.h83 struct dml2_soc_bb soc_bb; member

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