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Searched refs:soff (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/engine/disp/
A Dgt215.c38 const u32 soff = ior->id * 0x800; in gt215_sor_hda_eld() local
44 nvkm_wr32(device, 0x61c440 + soff, (i << 8)); in gt215_sor_hda_eld()
71 const u32 soff = nv50_ior_base(sor); in gt215_sor_dp_audio() local
100 const u32 soff = nv50_ior_base(ior); in gt215_sor_hdmi_infoframe_vsi() local
123 const u32 soff = nv50_ior_base(ior); in gt215_sor_hdmi_infoframe_avi() local
148 const u32 soff = nv50_ior_base(ior); in gt215_sor_hdmi_ctrl() local
189 const u32 soff = nv50_ior_base(ior); in gt215_sor_bl_set() local
192 div = nvkm_rd32(device, 0x61c080 + soff); in gt215_sor_bl_set()
204 const u32 soff = nv50_ior_base(ior); in gt215_sor_bl_get() local
207 div = nvkm_rd32(device, 0x61c080 + soff); in gt215_sor_bl_get()
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A Dg94.c57 const u32 soff = nv50_ior_base(sor); in g94_sor_dp_audio_sym() local
59 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h); in g94_sor_dp_audio_sym()
60 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v); in g94_sor_dp_audio_sym()
105 const u32 soff = nv50_ior_base(sor); in g94_sor_dp_power() local
124 const u32 soff = nv50_ior_base(sor); in g94_sor_dp_links() local
156 const u32 soff = nv50_ior_base(sor); in g94_sor_war_needed() local
204 const u32 soff = nv50_ior_base(sor); in g94_sor_war_3() local
210 sorpwr = nvkm_rd32(device, 0x61c004 + soff); in g94_sor_war_3()
212 u32 seqctl = nvkm_rd32(device, 0x61c030 + soff); in g94_sor_war_3()
245 const u32 soff = nv50_ior_base(sor); in g94_sor_war_2() local
[all …]
A Dgm107.c35 const u32 soff = nv50_ior_base(sor); in gm107_sor_dp_pattern() local
50 nvkm_mask(device, 0x61c110 + soff, mask, data); in gm107_sor_dp_pattern()
52 nvkm_mask(device, 0x61c12c + soff, mask, data); in gm107_sor_dp_pattern()
A Dgf119.c49 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_eld() local
53 nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | data[i]); in gf119_sor_hda_eld()
55 nvkm_wr32(device, 0x10ec00 + soff, (i << 8)); in gf119_sor_hda_eld()
56 nvkm_mask(device, 0x10ec10 + soff, 0x80000002, 0x80000002); in gf119_sor_hda_eld()
63 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_hpd() local
74 nvkm_mask(device, 0x10ec10 + soff, mask, data); in gf119_sor_hda_hpd()
154 const u32 soff = nv50_ior_base(sor); in gf119_sor_dp_pattern() local
167 nvkm_mask(device, 0x61c110 + soff, 0x1f1f1f1f, data); in gf119_sor_dp_pattern()
174 const u32 soff = nv50_ior_base(sor); in gf119_sor_dp_links() local
186 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); in gf119_sor_dp_links()
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A Dga102.c36 const u32 soff = nv50_ior_base(sor); in ga102_sor_dp_links() local
61 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); in ga102_sor_dp_links()
65 nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000); in ga102_sor_dp_links()
A Dtu102.c47 const u32 soff = nv50_ior_base(sor); in tu102_sor_dp_links() local
59 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); in tu102_sor_dp_links()
63 nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000); in tu102_sor_dp_links()
A Dnv50.c165 const u32 soff = nv50_ior_base(ior); in nv50_sor_bl_set() local
169 nvkm_wr32(device, 0x61c084 + soff, 0x80000000 | val); in nv50_sor_bl_set()
177 const u32 soff = nv50_ior_base(ior); in nv50_sor_bl_get() local
181 val = nvkm_rd32(device, 0x61c084 + soff); in nv50_sor_bl_get()
197 const u32 soff = nv50_ior_base(sor); in nv50_sor_clock() local
203 nv50_sor_power_wait(struct nvkm_device *device, u32 soff) in nv50_sor_power_wait() argument
206 if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000)) in nv50_sor_power_wait()
215 const u32 soff = nv50_ior_base(sor); in nv50_sor_power() local
220 nv50_sor_power_wait(device, soff); in nv50_sor_power()
221 nvkm_mask(device, 0x61c004 + soff, field, state); in nv50_sor_power()
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A Dgm200.c75 const u32 soff = nv50_ior_base(ior); in gm200_sor_hdmi_scdc() local
87 nvkm_mask(device, 0x61c5bc + soff, 0x00000003, ctrl); in gm200_sor_hdmi_scdc()
A Dgv100.c343 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_dmac_idle() local
345 u32 stat = nvkm_rd32(device, 0x610664 + soff); in gv100_disp_dmac_idle()
558 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_curs_idle() local
560 u32 stat = nvkm_rd32(device, 0x610664 + soff); in gv100_disp_curs_idle()
/drivers/dma/
A Dfsl-edma-common.c497 fsl_edma_set_tcd_to_le(fsl_chan, tcd, soff, soff); in fsl_edma_fill_tcd()
597 u16 soff, doff, iter; in fsl_edma_prep_dma_cyclic() local
638 soff = fsl_chan->cfg.dst_addr_width; in fsl_edma_prep_dma_cyclic()
648 soff = fsl_chan->cfg.src_addr_width; in fsl_edma_prep_dma_cyclic()
653 soff = doff = 0; in fsl_edma_prep_dma_cyclic()
675 u16 soff, doff, iter; in fsl_edma_prep_slave_sg() local
707 soff = fsl_chan->cfg.dst_addr_width; in fsl_edma_prep_slave_sg()
712 soff = 0; in fsl_edma_prep_slave_sg()
718 soff = 0; in fsl_edma_prep_slave_sg()
748 dst_addr, fsl_chan->attr, soff, in fsl_edma_prep_slave_sg()
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A Dfsl-edma-trace.h67 __field(u16, soff)
81 __entry->soff = fsl_edma_get_tcd_to_cpu(chan, tcd, soff),
105 __entry->soff,
A Dmpc512x_dma.c140 u32 soff:16; /* Signed source address offset */ member
635 tcd->soff = 32; in mpc_dma_prep_memcpy()
641 tcd->soff = 16; in mpc_dma_prep_memcpy()
646 tcd->soff = 4; in mpc_dma_prep_memcpy()
651 tcd->soff = 2; in mpc_dma_prep_memcpy()
656 tcd->soff = 1; in mpc_dma_prep_memcpy()
748 tcd->soff = 0; in mpc_dma_prep_slave_sg()
757 tcd->soff = mchan->swidth; in mpc_dma_prep_slave_sg()
A Dfsl-edma-common.h93 __le16 soff; member
107 __le16 soff; member
/drivers/pinctrl/qcom/
A Dpinctrl-lpass-lpi.h46 #define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ argument
49 .slew_offset = soff, \
/drivers/net/ethernet/netronome/nfp/bpf/
A Dverifier.c105 unsigned int soff; in nfp_bpf_map_update_value_ok() local
107 soff = -(off + i) - 1; in nfp_bpf_map_update_value_ok()
108 stack_entry = &state->stack[soff / BPF_REG_SIZE]; in nfp_bpf_map_update_value_ok()
109 if (stack_entry->slot_type[soff % BPF_REG_SIZE] == STACK_ZERO) in nfp_bpf_map_update_value_ok()
114 i, soff); in nfp_bpf_map_update_value_ok()
/drivers/gpu/drm/nouveau/dispnv04/
A Doverlay.c128 int soff = NV_PCRTC0_SIZE * nv_crtc->index; in nv10_update_plane() local
151 nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY); in nv10_update_plane()
/drivers/net/ethernet/intel/libeth/
A Dxdp.c88 libeth_xdp_return_frags(frm->data + frm->soff, true); in libeth_xdp_tx_return_one()
/drivers/block/aoe/
A Daoecmd.c1027 int soff = 0; in bvcpy() local
1034 skb_copy_bits(skb, soff, p, bv.bv_len); in bvcpy()
1036 soff += bv.bv_len; in bvcpy()
/drivers/crypto/
A Dhifn_795x.c1310 unsigned int soff, doff; in hifn_setup_dma() local
1316 soff = src->offset; in hifn_setup_dma()
1319 hifn_setup_src_desc(dev, spage, soff, len, n - len == 0); in hifn_setup_dma()
/drivers/net/ethernet/brocade/bna/
A Dbfa_ioc.c2190 bfa_nw_ioc_smem_read(struct bfa_ioc *ioc, void *tbuf, u32 soff, u32 sz) in bfa_nw_ioc_smem_read() argument
2196 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff); in bfa_nw_ioc_smem_read()
2197 loff = PSS_SMEM_PGOFF(soff); in bfa_nw_ioc_smem_read()
/drivers/scsi/bfa/
A Dbfa_ioc.c2039 bfa_ioc_smem_read(struct bfa_ioc_s *ioc, void *tbuf, u32 soff, u32 sz) in bfa_ioc_smem_read() argument
2046 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff); in bfa_ioc_smem_read()
2047 loff = PSS_SMEM_PGOFF(soff); in bfa_ioc_smem_read()
2098 bfa_ioc_smem_clr(struct bfa_ioc_s *ioc, u32 soff, u32 sz) in bfa_ioc_smem_clr() argument
2103 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff); in bfa_ioc_smem_clr()
2104 loff = PSS_SMEM_PGOFF(soff); in bfa_ioc_smem_clr()
/drivers/net/ethernet/sun/
A Dcassini.h2125 u8 soff, snext; /* if match succeeds, new offset and match */ member
A Dcassini.c1165 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff); in cas_load_firmware()

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